{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T05:33:59Z","timestamp":1740548039001,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":19,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540230953"},{"type":"electronic","value":"9783540302056"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30205-6_77","type":"book-chapter","created":{"date-parts":[[2010,9,21]],"date-time":"2010-09-21T21:00:42Z","timestamp":1285102842000},"page":"750-759","source":"Crossref","is-referenced-by-count":0,"title":["Buffer Sizing for Crosstalk Induced Delay Uncertainty"],"prefix":"10.1007","author":[{"given":"Dimitrios","family":"Velenis","sequence":"first","affiliation":[]},{"given":"Eby G.","family":"Friedman","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"77_CR1","doi-asserted-by":"crossref","unstructured":"Zarkesh-Ha, P., Mule, T., Meindl, J.D.: Characterization and Modeling of Clock Skew with Process Variations. In: Proceedings of the IEEE Custom Integrated Circuits Conference, May 1999, pp. 441\u2013444 (1999)","DOI":"10.1109\/CICC.1999.777319"},{"key":"77_CR2","unstructured":"Nassif, S.R.: Modeling and Analysis of Manufacturing Variations. In: Proceedings of the IEEE Custom Integrated Circuits Conference, May 2001, pp. 223\u2013228 (2001)"},{"issue":"4","key":"77_CR3","doi-asserted-by":"publisher","first-page":"403","DOI":"10.1109\/66.806117","volume":"12","author":"M. Orshansky","year":"1999","unstructured":"Orshansky, M., Chen, J.C., Hu, C.: Direct Sampling Methodology for Statistical Analysis of Scaled CMOS Technologies. IEEE Transactions on Semiconductor Manufacturing\u00a012(4), 403\u2013408 (1999)","journal-title":"IEEE Transactions on Semiconductor Manufacturing"},{"key":"77_CR4","doi-asserted-by":"crossref","unstructured":"Mehrotra, V., Sam, S.L., Boning, D., Chandrakasan, A., Vallishayee, R., Nassif, S.: A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance. In: Proceedings of the ACM\/IEEE Design Automation Conference, June 2000, pp. 172\u2013175 (2000)","DOI":"10.1145\/337292.337370"},{"issue":"4","key":"77_CR5","doi-asserted-by":"publisher","first-page":"401","DOI":"10.1109\/66.892625","volume":"13","author":"S. Zanella","year":"2000","unstructured":"Zanella, S., Nardi, A., Neviani, A., Quarantelli, M., Saxena, S., Guardiani, C.: Analysis of the Impact of Process Variations on Clock Skew. IEEE Transactions on Semiconductor Manufacturing\u00a013(4), 401\u2013407 (2000)","journal-title":"IEEE Transactions on Semiconductor Manufacturing"},{"issue":"4","key":"77_CR6","doi-asserted-by":"publisher","first-page":"395","DOI":"10.1109\/66.892624","volume":"13","author":"S. Sauter","year":"2000","unstructured":"Sauter, S., Schmitt-Landsiedel, D., Thewes, R., Weber, W.: Effect of Parameter Variations at Chip and Wafer Level on Clock Skews. IEEE Transactions on Semiconductor Manufacturing\u00a013(4), 395\u2013400 (2000)","journal-title":"IEEE Transactions on Semiconductor Manufacturing"},{"key":"77_CR7","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-4411-1","volume-title":"Timing Optimization Through Clock Skew Scheduling","author":"I.S. Kourtev","year":"2000","unstructured":"Kourtev, I.S., Friedman, E.G.: Timing Optimization Through Clock Skew Scheduling. Kluwer Academic Publishers, Norwell (2000)"},{"key":"77_CR8","doi-asserted-by":"crossref","unstructured":"Neves, J.L., Friedman, E.G.: Optimal Clock Skew Scheduling Tolerant to Process Variations. In: Proceedings of the ACM\/IEEE Design Automation Conference, June 1996, pp. 623\u2013628 (1996)","DOI":"10.1145\/240518.240636"},{"issue":"2","key":"77_CR9","doi-asserted-by":"publisher","first-page":"161","DOI":"10.1109\/92.585214","volume":"5","author":"M. Nekili","year":"1997","unstructured":"Nekili, M., Bois, C., Savaria, Y.: Pipelined H-Trees for High-Speed Clocking of Large Integrated Systems in Presence of Process Variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems\u00a05(2), 161\u2013174 (1997)","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"77_CR10","doi-asserted-by":"crossref","unstructured":"Velenis, D., Papaefthymiou, M.C., Friedman, E.G.: Reduced Delay Uncertainty in High Performance Clock Distribution Networks. In: Proceedings of the IEEE Design Automation and Test in Europe Conference, March 2003, pp. 68\u201373 (2003)","DOI":"10.1109\/DATE.2003.1253589"},{"key":"77_CR11","doi-asserted-by":"crossref","unstructured":"Tang, K.T., Friedman, E.G.: Interconnect Coupling Noise in CMOS VLSI Circuits. In: Proceedings of the ACM International Symposium on Physical Design, April 1999, pp. 48\u201353 (1999)","DOI":"10.1145\/299996.300020"},{"issue":"12","key":"77_CR12","doi-asserted-by":"publisher","first-page":"1817","DOI":"10.1109\/43.811330","volume":"18","author":"A. Vittal","year":"1999","unstructured":"Vittal, A., Chen, L.H., Marek-Sadowska, M., Wang, K.-P., Yang, S.: Crosstalk in VLSI Interconnections. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a018(12), 1817\u20131824 (1999)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"5","key":"77_CR13","doi-asserted-by":"publisher","first-page":"550","DOI":"10.1109\/43.845079","volume":"19","author":"S.S. Sapatnekar","year":"2000","unstructured":"Sapatnekar, S.S.: A Timing Model Incorporating the Effect of Crosstalk on Delay and its Application to Optimal Channel Routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a019(5), 550\u2013559 (2000)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"77_CR14","unstructured":"Huang, X., Cao, Y., Sylvester, D., Lin, S., King, T.-J., Hu, C.: RLC Signal Integrity Analysis of High Global Interconnects. In: Proceedings of the IEEE International Electron Devices Meeting, December 2000, pp. 731\u2013734 (2000)"},{"issue":"2","key":"77_CR15","doi-asserted-by":"publisher","first-page":"131","DOI":"10.1016\/S0167-9260(00)00005-5","volume":"29","author":"K.T. Tang","year":"2000","unstructured":"Tang, K.T., Friedman, E.G.: Delay and Noise Estimation of CMOS Logic Gates Driving Coupled Resistive-Capacitive Interconnections. Integration, the VLSI Journal\u00a029(2), 131\u2013165 (2000)","journal-title":"Integration, the VLSI Journal"},{"key":"77_CR16","unstructured":"Cong, J., Pan, D.Z., Srinivas, P.V.: Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization. In: Proceedings of the ACM\/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, December 2000, pp. 14\u201320 (2000)"},{"issue":"7","key":"77_CR17","doi-asserted-by":"publisher","first-page":"858","DOI":"10.1109\/43.931008","volume":"20","author":"M. Kuhlmann","year":"2001","unstructured":"Kuhlmann, M., Sapatnekar, S.S.: Exact and Efficient Crosstalk Estimation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a020(7), 858\u2013866 (2001)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"1","key":"77_CR18","doi-asserted-by":"publisher","first-page":"118","DOI":"10.1109\/16.249433","volume":"40","author":"T. Sakurai","year":"1993","unstructured":"Sakurai, T.: Closed-Form Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI\u2019s. IEEE Transactions on Electron Devices\u00a040(1), 118\u2013124 (1993)","journal-title":"IEEE Transactions on Electron Devices"},{"issue":"2","key":"77_CR19","doi-asserted-by":"publisher","first-page":"584","DOI":"10.1109\/4.52187","volume":"25","author":"T. Sakurai","year":"1990","unstructured":"Sakurai, T., Newton, A.R.: Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas. IEEE Journal of Solid State Circuits\u00a025(2), 584\u2013593 (1990)","journal-title":"IEEE Journal of Solid State Circuits"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30205-6_77.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,25]],"date-time":"2025-02-25T23:49:19Z","timestamp":1740527359000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30205-6_77"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540230953","9783540302056"],"references-count":19,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30205-6_77","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}