{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T20:03:30Z","timestamp":1725566610521},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540230953"},{"type":"electronic","value":"9783540302056"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30205-6_79","type":"book-chapter","created":{"date-parts":[[2010,9,21]],"date-time":"2010-09-21T21:00:42Z","timestamp":1285102842000},"page":"770-779","source":"Crossref","is-referenced-by-count":0,"title":["A New Logic Transformation Method for Both Low Power and High Testability"],"prefix":"10.1007","author":[{"given":"Y. S.","family":"Son","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. W.","family":"Na","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"79_CR1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-2307-9","volume-title":"Low Power Design Methodologies","author":"J.M. Rabaey","year":"1996","unstructured":"Rabaey, J.M., Pedram, M.: Low Power Design Methodologies, 1st edn. Kluwer Academic Publishers, Dordrecht (1996)","edition":"1"},{"key":"79_CR2","doi-asserted-by":"crossref","unstructured":"Rohfleisch, B., Kolbl, A., Wruth, B.: Reducing Power Dissipation after Technology Mapping by Structural Transformations. In: Proc. DAC, pp. 789\u2013794 (1996)","DOI":"10.1145\/240518.240667"},{"issue":"12","key":"79_CR3","doi-asserted-by":"crossref","first-page":"1494","DOI":"10.1109\/43.552082","volume":"15","author":"S. Chang","year":"1996","unstructured":"Chang, S., et al.: Multilevel Boolean Network Optimizer. IEEE Trans. CAD\u00a015(12), 1494\u20131504 (1996)","journal-title":"IEEE Trans. CAD"},{"key":"79_CR4","unstructured":"Cheng, K.T., Entrena, L.A.: Multi-level Logic Optimization By Redundancy Addition and Removal. In: Proc. European DAC, pp. 373\u2013337 (1993)"},{"key":"79_CR5","doi-asserted-by":"crossref","unstructured":"Wang, Q., Vrudhula, S.B.: Multi-level Logic Optimization for Low Power using Local Logic Transformations. In: Proc. ICCAD, pp. 270\u2013277 (1996)","DOI":"10.1109\/ICCAD.1996.569643"},{"key":"79_CR6","doi-asserted-by":"crossref","unstructured":"Chung, K.-S., Liu, C.L.: Local Transformation Techniques for Multi-Level Logic Circuits Utilizing Circuit Symmetries for Power Reductions. In: Proc. ISLPED, pp. 215\u2013220 (1998)","DOI":"10.1145\/280756.280904"},{"key":"79_CR7","doi-asserted-by":"crossref","unstructured":"Savir, J., Berry, R.: At-speed test is not necessarily an AC test. In: Proc. ITC, pp. 722\u2013728 (1991)","DOI":"10.1109\/TEST.1991.519737"},{"key":"79_CR8","doi-asserted-by":"crossref","unstructured":"Chaterjee, M., Pradhan, D.K.: A Novel Pattern Generator for Near-Perfect Fault-Coverage. In: Proc. VLSI Test Symp., pp. 417\u2013425 (1995)","DOI":"10.1109\/VTEST.1995.512669"},{"key":"79_CR9","doi-asserted-by":"publisher","first-page":"930","DOI":"10.1109\/12.536235","volume":"45","author":"J. Savir","year":"1996","unstructured":"Savir, J.: Reducing the MISR size. IEEE Trans. Comp.\u00a045, 930\u2013938 (1996)","journal-title":"IEEE Trans. Comp."},{"key":"79_CR10","doi-asserted-by":"crossref","unstructured":"AlShaibi, M.F., Kime, C.R.: MFBIST: A BIST Method for Random Pattern Resistant Circuits. In: Proc. ITC, pp. 176\u2013185 (1996)","DOI":"10.1109\/TEST.1996.556960"},{"key":"79_CR11","volume-title":"Built-In Test for VLSI : Pseudorandom Techniques","author":"P.H. Bardell","year":"1987","unstructured":"Bardell, P.H., McAnney, W.H., Savir, J.: Built-In Test for VLSI: Pseudorandom Techniques, 1st edn. John Wiley & Sons, Chichester (1987)","edition":"1"},{"key":"79_CR12","doi-asserted-by":"crossref","unstructured":"Goldstein, H.: Controllability\/observability of digital circuits. IEEE Trans. Circuits and Systems, 685\u2013693 (1979)","DOI":"10.1109\/TCS.1979.1084687"},{"key":"79_CR13","doi-asserted-by":"crossref","unstructured":"Costa, J.C., Monteiro, J.C., Devadas, S.: Switching Activity Estimation using Limited Depth Reconvergent Path Analysis. In: Proc. ISLPED, pp. 184\u2013189 (1997)","DOI":"10.1145\/263272.263323"},{"key":"79_CR14","unstructured":"Lee, H.K., Ha, D.S.: Atalanta: an Efficient ATPG for Combinational Circuits, Technical Report, pp. 93-12, Dept. of Electrical Eng., Virginia Polytechnic Institute and State University (1993)"},{"key":"79_CR15","unstructured":"Lee, H.K., Ha, D.S.: An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation. In: Proc. ITC, pp. 946\u2013955 (1991)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30205-6_79.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,19]],"date-time":"2020-11-19T04:48:30Z","timestamp":1605761310000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30205-6_79"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540230953","9783540302056"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30205-6_79","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}