{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T19:58:26Z","timestamp":1725566306762},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540236641"},{"type":"electronic","value":"9783540304708"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30470-8_52","type":"book-chapter","created":{"date-parts":[[2010,9,23]],"date-time":"2010-09-23T21:42:15Z","timestamp":1285278135000},"page":"371-382","source":"Crossref","is-referenced-by-count":34,"title":["A Time Predictable Instruction Cache for a Java Processor"],"prefix":"10.1007","author":[{"given":"Martin","family":"Schoeberl","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"52_CR1","doi-asserted-by":"publisher","first-page":"159","DOI":"10.1007\/BF00571421","volume":"1","author":"P. Puschner","year":"1989","unstructured":"Puschner, P., Koza, C.: Calculating the maximum execution time of real-time programs. Real-Time Syst.\u00a01, 159\u2013176 (1989)","journal-title":"Real-Time Syst."},{"key":"52_CR2","doi-asserted-by":"crossref","unstructured":"Arnold, R., Mueller, F., Whalley, D., Harmon, M.: Bounding worst-case instruction cache performance. In: IEEE Real-Time Systems Symposium, pp. 172\u2013181 (1994)","DOI":"10.1109\/REAL.1994.342718"},{"key":"52_CR3","doi-asserted-by":"crossref","unstructured":"Healy, C., Whalley, D., Harmon, M.: Integrating the timing analysis of pipelining and instruction caching. In: IEEE Real-Time Systems Symposium, pp. 288\u2013297 (1995)","DOI":"10.1109\/REAL.1995.495218"},{"key":"52_CR4","doi-asserted-by":"publisher","first-page":"700","DOI":"10.1109\/12.689649","volume":"47","author":"C.G. Lee","year":"1998","unstructured":"Lee, C.G., Hahn, J., Seo, Y.M., Min, S.L., Ha, R., Hong, S., Park, C.Y., Lee, M., Kim, C.S.: Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. IEEE Trans. Comput.\u00a047, 700\u2013713 (1998)","journal-title":"IEEE Trans. Comput."},{"key":"52_CR5","first-page":"204","volume-title":"IEEE Real-Time Technology and Applications Symposium (RTAS 1996)","author":"J.V. Busquets-Mataix","year":"1996","unstructured":"Busquets-Mataix, J.V., Wellings, A., Serrano, J.J., Ors, R., Gil, P.: Adding instruction cache effect to schedulability analysis of preemptive real-time systems. In: IEEE Real-Time Technology and Applications Symposium (RTAS 1996), Washington - Brussels - Tokyo, pp. 204\u2013213. IEEE Computer Society Press, Los Alamitos (1996)"},{"key":"52_CR6","doi-asserted-by":"crossref","unstructured":"Heckmann, R., Langenbach, M., Thesing, S., Wilhelm, R.: The influence of processor architecture on the design and results of WCET tools. Proceedings of the IEEE\u00a091 (2003)","DOI":"10.1109\/JPROC.2003.814618"},{"key":"52_CR7","unstructured":"Power, J., Waldron, J.: Amethod-level analysis of object-oriented techniques in java. Technical report, Department of Computer Science, NUI Maynooth, Ireland (2002)"},{"key":"52_CR8","first-page":"94303","volume-title":"Computer Architecture: A Quantitative Approach","author":"J. Hennessy","year":"2002","unstructured":"Hennessy, J., Patterson, D.: Computer Architecture: A Quantitative Approach, 3rd edn., Morgan Kaufmann Publishers Inc., Palo Alto, 94303 (2002)","edition":"3"},{"key":"52_CR9","unstructured":"Schoeberl, M.: Using a Java optimized processor in a real world application. In: Proceedings of the First Workshop on Intelligent Solutions in Embedded Systems (WISES 2003), Austria, Vienna, pp. 165\u2013176 (2003)"},{"key":"52_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"346","DOI":"10.1007\/978-3-540-39962-9_43","volume-title":"On The Move to Meaningful Internet Systems 2003: OTM 2003 Workshops","author":"M. Schoeberl","year":"2003","unstructured":"Schoeberl, M.: JOP: A Java optimized processor. In: Meersman, R., Tari, Z. (eds.) OTM-WS 2003. LNCS, vol.\u00a02889, pp. 346\u2013359. Springer, Heidelberg (2003)"}],"container-title":["Lecture Notes in Computer Science","On the Move to Meaningful Internet Systems 2004: OTM 2004 Workshops"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30470-8_52.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,3]],"date-time":"2021-05-03T04:02:16Z","timestamp":1620014536000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30470-8_52"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540236641","9783540304708"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30470-8_52","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}