{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T15:55:17Z","timestamp":1725551717191},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540237389"},{"type":"electronic","value":"9783540304944"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2004]]},"DOI":"10.1007\/978-3-540-30494-4_10","type":"book-chapter","created":{"date-parts":[[2010,6,29]],"date-time":"2010-06-29T14:42:14Z","timestamp":1277822534000},"page":"128-143","source":"Crossref","is-referenced-by-count":3,"title":["Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs"],"prefix":"10.1007","author":[{"given":"Laurent","family":"Arditi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gerard","family":"Berry","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael","family":"Kishinevsky","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"10_CR1","unstructured":"Andr\u00e9, C.: Representation and analysis of reactive behaviors: A synchronous approach. In: CESA 1996, Lille, France (July 1996)"},{"key":"10_CR2","doi-asserted-by":"publisher","first-page":"87","DOI":"10.1098\/rsta.1992.0027","volume":"339","author":"G. Berry","year":"1992","unstructured":"Berry, G.: Esterel on hardware. Philosophical Transactions Royal Society of London A\u00a0339, 87\u2013104 (1992)","journal-title":"Philosophical Transactions Royal Society of London A"},{"key":"10_CR3","unstructured":"Berry, G.: The Constructive Semantics of Pure Esterel. Draft book version 3 (July 1999), available at \n                  \n                    http:\/\/www.esterel.org"},{"key":"10_CR4","unstructured":"Brand, D., Drumm, A., Kundu, S., Narain, P.S.: Incremental synthesis. In: Proc. ICCAD (1994)"},{"key":"10_CR5","unstructured":"Coudert, O., Berthet, C., Madre, J.-C.: New ideas on symbolic manipulation of finite state machines. In: Proc. ICCAD (1990)"},{"key":"10_CR6","unstructured":"Coudert, O., Madre, J.-C., Touati, H.: Tiger 1.0 user manual. Technical report, Digital Equipment Paris Research Lab (1993)"},{"key":"10_CR7","doi-asserted-by":"crossref","unstructured":"Drini, M., Kirovski, D.: Behavioral synthesis via engineering change. In: Proc. DAC (2002)","DOI":"10.1145\/513918.513925"},{"key":"10_CR8","doi-asserted-by":"crossref","unstructured":"Hassoun, S.: Fine grain incremental rescheduling via architectural retiming. In: Proc. 11th International Symposium on System Synthesis (1998)","DOI":"10.1109\/ISSS.1998.730619"},{"issue":"5","key":"10_CR9","doi-asserted-by":"publisher","first-page":"443","DOI":"10.1109\/12.859539","volume":"49","author":"S.-Y. Huang","year":"2000","unstructured":"Huang, S.-Y., Cheng, K.-T., Chen, K.-C., Brewer, F., Huang, C.-Y.: Aquila: An equivalence checking system for large sequential designs. IEEE Trans. Comput.\u00a049(5), 443\u2013464 (2000)","journal-title":"IEEE Trans. Comput."},{"key":"10_CR10","unstructured":"Sarrafzadeh, M., Cong, J.: Incremental physical design. In: Proc. ISPD (2000)"},{"issue":"6","key":"10_CR11","doi-asserted-by":"publisher","first-page":"686","DOI":"10.1109\/TCAD.2003.811446","volume":"22","author":"J.-H.R. Jiang","year":"2003","unstructured":"Jiang, J.-H.R., Brayton, R.K.: On the verification of sequential equivalence. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems\u00a022(6), 686\u2013697 (2003)","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"10_CR12","doi-asserted-by":"crossref","unstructured":"Knapp, D.W.: Manual rescheduling and incremental repair of register-level datapaths. In: Proc. ICCAD (1989)","DOI":"10.1109\/ICCAD.1989.76904"},{"key":"10_CR13","doi-asserted-by":"crossref","unstructured":"Lin, C., Chen, K., Chang, S., Marek-Sadowska, M.: Logic synthesis for engineering change. In: Proc. DAC (1995)","DOI":"10.1145\/217474.217604"},{"key":"10_CR14","series-title":"Lecture Notes in Computer Science","first-page":"108","volume-title":"Formal Methods in Computer-Aided Design","author":"S. Singh","year":"2000","unstructured":"Singh, S., Sheeran, M., Stalmarck, G.: Checking safety properties using induction and a sat-solver. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol.\u00a01954, pp. 108\u2013125. Springer, Heidelberg (2000)"},{"key":"10_CR15","doi-asserted-by":"publisher","first-page":"770","DOI":"10.1145\/277044.277239","volume-title":"Proceedings of the 35th annual conference on Design automation conference","author":"A. Seawright","year":"1998","unstructured":"Seawright, A., Meyer, W.: Partitioning and optimizing controllers synthesized from hierarchical high-level descriptions. In: Proceedings of the 35th annual conference on Design automation conference, pp. 770\u2013775. ACM Press, New York (1998)"},{"key":"10_CR16","doi-asserted-by":"crossref","unstructured":"Sentovich, E., Toma, H., Berry, G.: Latch optimization in circuits generated from high-level descriptions. In: Proc. International Conf. on Computer-Aided Design ICCAD (1996)","DOI":"10.1109\/ICCAD.1996.569833"},{"key":"10_CR17","doi-asserted-by":"crossref","unstructured":"Sentovich, E., Toma, H., Berry, G.: Efficient latch optimization using exclusive sets. In: Proc. Digital Automation Conference DAC (1997)","DOI":"10.1109\/DAC.1997.597108"},{"key":"10_CR18","unstructured":"Sentovich, E.M., Singh, K.J., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P.R., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: SIS: A system for sequential circuit synthesis. Technical report, University of California at Berkeley (1992) Memorandum No. UCB\/ERL M92\/41"},{"key":"10_CR19","unstructured":"Touati, H., Berry, G.: Optimized controller synthesis using Esterel. In: Proc. International Workshop on Logic Synthesis, IWLS 1993, Lake Tahoe (1993)"},{"issue":"7","key":"10_CR20","doi-asserted-by":"publisher","first-page":"814","DOI":"10.1109\/43.851997","volume":"19","author":"C.A.J. Eijk van","year":"2000","unstructured":"van Eijk, C.A.J.: Sequential equivalence checking based on structural similarities. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems\u00a019(7), 814\u2013819 (2000)","journal-title":"IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems"},{"key":"10_CR21","doi-asserted-by":"crossref","unstructured":"Watanabe, Y., Brayton, R.K.: Incremental synthesis for engineering changes. In: Proc. ICCAD (1991)","DOI":"10.1109\/ICCD.1991.139840"}],"container-title":["Lecture Notes in Computer Science","Formal Methods in Computer-Aided Design"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-30494-4_10.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,3]],"date-time":"2021-05-03T00:04:32Z","timestamp":1620000272000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-30494-4_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004]]},"ISBN":["9783540237389","9783540304944"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-30494-4_10","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2004]]}}}