{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T10:14:56Z","timestamp":1742379296520},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540203599"},{"type":"electronic","value":"9783540397076"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39707-6_6","type":"book-chapter","created":{"date-parts":[[2010,6,29]],"date-time":"2010-06-29T15:34:42Z","timestamp":1277825682000},"page":"70-85","source":"Crossref","is-referenced-by-count":28,"title":["Improving Memory Latency Aware Fetch Policies for SMT Processors"],"prefix":"10.1007","author":[{"given":"Francisco J.","family":"Cazorla","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Enrique","family":"Fernandez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex","family":"Ram\u00edrez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"6_CR1","doi-asserted-by":"crossref","unstructured":"Cazorla, F.J., Fernandez, E., Ramirez, A., Valero, M.: Improving long-latencyloads- aware fetch policies for SMT processors. Technical Report UPC-DAC-2003- 21, Universitat Politecnica de Catalunya (May 2003)","DOI":"10.1007\/978-3-540-39707-6_6"},{"key":"6_CR2","doi-asserted-by":"crossref","unstructured":"El-Moursy, A., Albonesi, D.H.: Front-end policies for improved issue efficiency in SMT processors. In: Proceedings of the 9th Intl. Conference on High Performance Computer Architecture (February 2003)","DOI":"10.1109\/HPCA.2003.1183522"},{"key":"6_CR3","doi-asserted-by":"crossref","unstructured":"Gulati, M., Bagherzadeh, N.: Performance study of a multithreaded superscalar microprocessor. In: Proceedings of the 2nd Intl. Conference on High Performance Computer Architecture, February 1996, pp. 291\u2013301 (1996)","DOI":"10.1109\/HPCA.1996.501194"},{"key":"6_CR4","doi-asserted-by":"crossref","unstructured":"Limousin, C., S\u00e9bot, J., Vartanian, A., Drach-Temam, N.: Improving 3d geometry transformations on a simultaneous multithreaded SIMD processor. In: Proceedings of the 13th Intl. Conference on Supercomputing, May 2001, pp. 236\u2013245 (2001)","DOI":"10.1145\/377792.377839"},{"key":"6_CR5","unstructured":"Luo, K., Gummaraju, J., Franklin, M.: Balancing throughput and fairness in SMT processors. In: Proceedings of the International Symposium on Performance Analysis of Systems and Software, November 2001, pp. 164\u2013171 (2001)"},{"key":"6_CR6","doi-asserted-by":"crossref","unstructured":"Sherwood, T., Perelman, E., Calder, B.: Basic block distribution analysis to find periodic behavior and simulation points in applications. In: Proceedings of the Intl. Conference on Parallel Architectures and Compilation Techniques (September 2001)","DOI":"10.1109\/PACT.2001.953283"},{"key":"6_CR7","doi-asserted-by":"crossref","unstructured":"Tullsen, D., Brown, J.: Handling long-latency loads in a simultaneous multithreaded processor. In: Proceedings of the 34th Annual ACM\/IEEE Intl. Symposium on Microarchitecture (December 2001)","DOI":"10.1109\/MICRO.2001.991129"},{"key":"6_CR8","doi-asserted-by":"crossref","unstructured":"Tullsen, D., Eggers, S., Emer, J., Levy, H., Lo, J., Stamm, R.: Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In: Proceedings of the 23th Annual Intl. Symposium on Computer Architecture, April 1996, pp. 191\u2013202 (1996)","DOI":"10.1145\/232973.232993"},{"key":"6_CR9","doi-asserted-by":"crossref","unstructured":"Tullsen, D.M., Eggers, S., Levy, H.M.: Simultaneous multithreading: Maximizing on-chip parallelism. In: Proceedings of the 22th Annual Intl. Symposium on Computer Architecture (1995)","DOI":"10.1145\/223982.224449"},{"key":"6_CR10","unstructured":"Yamamoto, W., Nemirovsky, M.: Increasing superscalar performance through multistreaming. In: Proceedings of the 1st Intl. Conference on High Performance Computer Architecture, June 1995, pp. 49\u201358 (1995)"},{"key":"6_CR11","doi-asserted-by":"crossref","unstructured":"Yoaz, A., Erez, M., Ronen, R., Jourdan, S.: Speculation techniques for improving load related instruction scheduling. In: Proceedings of the 26th Annual Intl. Symposium on Computer Architecture (May 1999)","DOI":"10.1109\/ISCA.1999.765938"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39707-6_6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,30]],"date-time":"2019-05-30T11:00:59Z","timestamp":1559214059000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39707-6_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540203599","9783540397076"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39707-6_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}