{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T18:14:35Z","timestamp":1725560075281},"publisher-location":"Berlin, Heidelberg","reference-count":13,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540200741"},{"type":"electronic","value":"9783540397625"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39762-5_20","type":"book-chapter","created":{"date-parts":[[2010,7,22]],"date-time":"2010-07-22T23:08:02Z","timestamp":1279840082000},"page":"181-191","source":"Crossref","is-referenced-by-count":8,"title":["Static Implementation of QDI Asynchronous Primitives"],"prefix":"10.1007","author":[{"given":"P.","family":"Maurine","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J. B.","family":"Rigaud","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Bouesse","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Sicard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Renaudin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"20_CR1","doi-asserted-by":"crossref","unstructured":"Chelcea, T., Bardsley, A., Edwards, D.A., Nowick, S.M.: A Burst-Mode Oriented Back-End for the Balsa Synthesis System. In: Proceedings of DATE 2002, Paris, March 2002, pp. 330\u2013337 (2002)","DOI":"10.1109\/DATE.2002.998294"},{"issue":"3","key":"20_CR2","first-page":"315","volume":"E80-D","author":"J. Cortadella","year":"1997","unstructured":"Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Transactions on Information and Systems\u00a0E80-D(3), 315\u2013325 (1997)","journal-title":"IEICE Transactions on Information and Systems"},{"key":"20_CR3","unstructured":"Renaudin, M., et al.: TAST. In: Tutorial given at the 8th international Symposium on Advanced Research in Asynchronous Circuits and Systems, Manchester, UK (April 8-11, 2002)"},{"key":"20_CR4","doi-asserted-by":"publisher","first-page":"584","DOI":"10.1109\/4.52187","volume":"25","author":"T. Sakurai","year":"1990","unstructured":"Sakurai, T., Newton, A.R.: Alpha-power model, and its application to CMOS inverter delay and other formulas. J. of Solid State Circuits\u00a025, 584\u2013594 (1990)","journal-title":"J. of Solid State Circuits"},{"key":"20_CR5","doi-asserted-by":"crossref","unstructured":"Maurine, P., Rezzoug, M., Azemard, N., Auvergne, D.: Transition Time modelling in Deep Submicron CMOS. IEEE trans. on CAD of IC and Systems\u00a021(1) (November 2002)","DOI":"10.1109\/TCAD.2002.804088"},{"key":"20_CR6","doi-asserted-by":"crossref","unstructured":"Chatzigeorgiou, A., Nikolaidis, S., Tsoukalas, I.: A modelling technique for CMOS gates. IEEE Trans on CAD oflntegrated Circuits and Systems\u00a018(5) (May 1999)","DOI":"10.1109\/43.759070"},{"issue":"1","key":"20_CR7","doi-asserted-by":"publisher","first-page":"99","DOI":"10.1109\/92.365457","volume":"3","author":"B.S. Cherkauer","year":"1995","unstructured":"Cherkauer, B.S., Friedman, E.G.: A Unified Design Methodology for CMOS Tapered Buffers. IEEE Transactions on VLSI Systems\u00a03(1), 99\u2013111 (1995)","journal-title":"IEEE Transactions on VLSI Systems"},{"issue":"2","key":"20_CR8","doi-asserted-by":"crossref","first-page":"270","DOI":"10.1109\/TCAD.1987.1270271","volume":"CAD-6","author":"N. Hedenstierna","year":"1987","unstructured":"Hedenstierna, N., Jeppson, K.O.: CMOS Circuit Speed and Buffer Optimization. IEEE transactions on CAD\u00a0CAD-6(2), 270\u2013281 (1987)","journal-title":"IEEE transactions on CAD"},{"key":"20_CR9","unstructured":"Piguet, C., Zhand, J.: Electrical Design of Dynamic and Static Speed Independent CMOS Circuits from Signal Transistion Graphs. In: PATMOS 1998, pp. 357\u2013366 (1998)"},{"key":"20_CR10","volume-title":"Logical Effort: Designing Fast CMOS Circuits","author":"I. Sutherland","year":"1999","unstructured":"Sutherland, I., Sproull, B., Harris, D.: Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann Publishers, Inc., San Francisco (1999)"},{"key":"20_CR11","volume-title":"introduction to VLSI","author":"C. Mead","year":"1980","unstructured":"Mead, C., Conway, N.: introduction to VLSI. Addison Wesley, Reading (1980)"},{"key":"#cr-split#-20_CR12.1","doi-asserted-by":"crossref","unstructured":"Renaudin, M.: Asynchronous Circuits and Systems: a promising design alternative. In: Microelectronics for Telecommunications: managing high complexity and mobility, MIGAS 2000 (2000);","DOI":"10.1016\/S0167-9317(00)80065-9"},{"key":"#cr-split#-20_CR12.2","doi-asserted-by":"crossref","unstructured":"Special issue of the Microelectronics-Engineering Journal. Elsevier Science, Guest Editors : Senn, P., Renaudin, M., Boussey, J. vol. 54(1-2), pp. 133???149 (December 2000)","DOI":"10.1016\/S0167-9317(00)80065-9"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39762-5_20","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T04:56:13Z","timestamp":1635742573000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39762-5_20"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540200741","9783540397625"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39762-5_20","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}