{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T18:15:14Z","timestamp":1725560114538},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540200741"},{"type":"electronic","value":"9783540397625"}],"license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39762-5_28","type":"book-chapter","created":{"date-parts":[[2010,7,22]],"date-time":"2010-07-22T19:08:02Z","timestamp":1279825682000},"page":"219-228","source":"Crossref","is-referenced-by-count":8,"title":["Energy Efficient Register Renaming"],"prefix":"10.1007","author":[{"given":"Gurhan","family":"Kucuk","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oguz","family":"Ergin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dmitry","family":"Ponomarev","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kanad","family":"Ghose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"28_CR1","doi-asserted-by":"crossref","unstructured":"Burger, D., Austin, T.M.: The SimpleScalar tool set: Version 2.0., Tech. Report, Dept. of CS, Univ. of Wisconsin\u2013Madison, and documentation for all Simplescalar releases (June 1997)","DOI":"10.1145\/268806.268810"},{"key":"28_CR2","doi-asserted-by":"crossref","unstructured":"Cruz, J.\u2013L., Gonzalez, A., Valero, M., et al.: Multiple\u2013Banked Register File Architecture. In: Proceedings 27th International Symposium on Computer Architecture, pp. 316\u2013325 (2000)","DOI":"10.1145\/342001.339708"},{"key":"28_CR3","unstructured":"Ergin, O., et al.: A Circuit\u2013Level Implementation of Fast, Energy\u2013Efficient CMOS Comparators for High\u2013Performance Microprocessors. In: Proceedings of ICCD (2002)"},{"key":"28_CR4","doi-asserted-by":"crossref","unstructured":"Folegnani, D., Gonzalez, A.: Energy\u2013Effective Issue Logic. In: Proceedings of International Symposium on Computer Architecture (July 2001)","DOI":"10.1145\/379240.379266"},{"key":"28_CR5","doi-asserted-by":"crossref","unstructured":"Ghose, K., Kamble, M.: Reducing Power in Superscalar Processor Caches Using Subbanking, Multiple Line Buffers and Bit\u2013Line Segmentation. In: Proceedings of International Symposium on Low Power Electronics and Design (ISLPED 1999), August 1999, pp. 70\u201375 (1999)","DOI":"10.1145\/313817.313860"},{"key":"28_CR6","doi-asserted-by":"crossref","unstructured":"Liu, T., Lu, S.: Performance Improvement with Circuit Level Speculation. In: Proceedings of the 33rd International Symposium on Microarchitecture (2000)","DOI":"10.1145\/360128.360166"},{"issue":"2","key":"28_CR7","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/40.755465","volume":"19","author":"R.E. Kessler","year":"1999","unstructured":"Kessler, R.E.: The Alpha 21264 Microprocessor. IEEE Micro\u00a019(2), 24\u201336 (1999)","journal-title":"IEEE Micro"},{"key":"28_CR8","doi-asserted-by":"crossref","unstructured":"Manne, S., Klauser, A., Grunwald, D.: Pipeline Gating: Speculation Control for Energy Reduction. In: Proceedings of the 25th International Symposium on Computer Architecture (ISCA), pp. 132\u2013141 (1998)","DOI":"10.1145\/279361.279377"},{"key":"28_CR9","unstructured":"Moshovos, A.: Power\u2013Aware Register Renaming. Technical Report, University of Toronto (August 2002)"},{"key":"28_CR10","unstructured":"Ponomarev, D., Kucuk, G., Ghose, K.: AccuPower: an Accurate Power Estimation Tool for Superscalar Microprocessors. In: Proceedings of 5th Design, Automation and Test in Europe Conference (DATE-2002) (March 2002)"},{"key":"28_CR11","unstructured":"Pollack, F.: New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies. In: 32nd International Symposium on Microarchitecture (November 1999) (keynote presentation)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39762-5_28","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,19]],"date-time":"2019-05-19T16:29:25Z","timestamp":1558283365000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39762-5_28"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540200741","9783540397625"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39762-5_28","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}