{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T18:15:29Z","timestamp":1725560129975},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540200741"},{"type":"electronic","value":"9783540397625"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39762-5_31","type":"book-chapter","created":{"date-parts":[[2010,7,22]],"date-time":"2010-07-22T23:08:02Z","timestamp":1279840082000},"page":"249-258","source":"Crossref","is-referenced-by-count":4,"title":["A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems"],"prefix":"10.1007","author":[{"given":"Gianluca","family":"Palermo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cristina","family":"Silvano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vittorio","family":"Zaccaria","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"31_CR1","doi-asserted-by":"crossref","unstructured":"Su, C.L., Despain, A.M.: Cache design trade-offs for power and performance optimization: A case study. In: ISLPED-1995: ACM\/IEEE Int. Symposium on Low Power Electronics and Design (1995)","DOI":"10.1145\/224081.224093"},{"key":"31_CR2","doi-asserted-by":"crossref","unstructured":"Li, Y., Henkel, J.: A framework for estimating and minimizing energy dissipation of embedded hw\/sw systems. In: DAC-35: ACM\/IEEE Design Automation Conference (June 1998)","DOI":"10.1145\/277044.277097"},{"key":"31_CR3","doi-asserted-by":"crossref","unstructured":"Kin, J.K., Gupta, M., Mangione-Smith, W.H.: Filtering Memory References to Increase Energy Efficiency. IEEE Trans. on Computers\u00a049(1) (January 2000)","DOI":"10.1109\/12.822560"},{"issue":"2","key":"31_CR4","doi-asserted-by":"publisher","first-page":"129","DOI":"10.1109\/92.831433","volume":"8","author":"T.M. Conte","year":"2000","unstructured":"Conte, T.M., Menezes, K.N., Sathaye, S.W., Toburen, M.C.: System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. on Very Large Scale Integration (VLSI) Systems\u00a08(2), 129\u2013137 (2000)","journal-title":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems"},{"key":"31_CR5","unstructured":"Burger, D., Austin, T.M., Bennett, S.: Evaluating future microprocessors: The simplescalar tool set. Technical Report CS-TR-1996-1308, University of Wisconsin (1996)"},{"key":"31_CR6","doi-asserted-by":"crossref","unstructured":"Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: Proceedings ISCA 2000, pp. 83\u201394 (2000)","DOI":"10.1145\/339647.339657"},{"key":"31_CR7","doi-asserted-by":"crossref","unstructured":"Bellas, N., Hajj, I.N., Polychronopoulos, D., Stamoulis, G.: Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Transactions on Very Large Scale of Integration (VLSI) Systems 8(3) (June 2000)","DOI":"10.1109\/92.845897"},{"key":"31_CR8","doi-asserted-by":"crossref","unstructured":"Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Kim, H.S., Ye, W.: Energy-driven integrated hardware-software optimizations using simple power. In: ISCA 2000: 2000 International Symposium on Computer Architecture, Vancouver BC, Canada (June 2000)","DOI":"10.1145\/339647.339659"},{"issue":"11","key":"31_CR9","doi-asserted-by":"publisher","first-page":"1317","DOI":"10.1109\/TCAD.2002.804107","volume":"21","author":"T.D. Givargis","year":"2002","unstructured":"Givargis, T.D., Vahid, F.: Platune: a tuning framework for system-on-achip platforms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a021(11), 1317\u20131327 (2002)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"31_CR10","unstructured":"Palesi, M., Givargis, T.: Multi-objective design space exploration using genetic lgorithms. In: Proceedings of the Tenth International Symposium on Hardware\/ Software Codesign 2002, CODES 2002 (May 6\u20138, 2002)"},{"key":"31_CR11","volume-title":"High-Level Synthesis, Introduction to Chip and System Design","author":"D. Gajski","year":"1994","unstructured":"Gajski, D., Dutt, N., Wu, A., Lin, S.: High-Level Synthesis, Introduction to Chip and System Design. Kluwer Academic Publishers, Dordrecht (1994)"},{"issue":"12","key":"31_CR12","doi-asserted-by":"publisher","first-page":"1523","DOI":"10.1109\/43.898830","volume":"19","author":"K. Keutzer","year":"2000","unstructured":"Keutzer, K., Malik, S., Newton, A.R., Rabaey, J., Sangiovanni-Vincentelli, A.: System level design: Orthogonolization of concerns and platform-based design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a019(12), 1523\u20131543 (2000)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"31_CR13","volume-title":"Data Structures and Algorithms","author":"A. Aho","year":"1983","unstructured":"Aho, A., Hopcroft, J., Ullman, J.: Data Structures and Algorithms. Addison-Wesley, Reading (1983)"},{"key":"31_CR14","doi-asserted-by":"crossref","DOI":"10.1007\/978-94-011-3436-1","volume-title":"Theory of global random search","author":"A.A. Zhigljavsky","year":"1991","unstructured":"Zhigljavsky, A.A.: Theory of global random search, vol.\u00a065. Kluwer Academic publishers Group, Dordrecht (1991)"},{"key":"31_CR15","doi-asserted-by":"publisher","first-page":"34","DOI":"10.1002\/(SICI)1099-1360(199801)7:1<34::AID-MCDA161>3.0.CO;2-6","volume":"7","author":"A. Jaszkiewicz","year":"1998","unstructured":"Jaszkiewicz, A., Czyak, P.: Pareto simulated annealing - a metaheuristic technique for multiple-objective combinatorial optimisation. Journal of Multi-Criteria Decision Analysis\u00a0(7), 34\u201347 (1998)","journal-title":"Journal of Multi-Criteria Decision Analysis"},{"issue":"2","key":"31_CR16","doi-asserted-by":"crossref","first-page":"126","DOI":"10.1287\/ijoc.6.2.126","volume":"6","author":"R. Battiti","year":"1994","unstructured":"Battiti, R., Tecchiolli, G.: The reactive tabu search. ORSA Journal on Computing\u00a06(2), 126\u2013140 (1994)","journal-title":"ORSA Journal on Computing"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39762-5_31","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,31]],"date-time":"2019-05-31T12:58:49Z","timestamp":1559307529000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39762-5_31"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540200741","9783540397625"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39762-5_31","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}