{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T18:15:34Z","timestamp":1725560134077},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540200741"},{"type":"electronic","value":"9783540397625"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39762-5_46","type":"book-chapter","created":{"date-parts":[[2010,7,22]],"date-time":"2010-07-22T23:08:02Z","timestamp":1279840082000},"page":"399-408","source":"Crossref","is-referenced-by-count":2,"title":["Energy Optimization of High-Performance Circuits"],"prefix":"10.1007","author":[{"given":"Hoang Q.","family":"Dao","sequence":"first","affiliation":[]},{"given":"Bart R.","family":"Zeydel","sequence":"additional","affiliation":[]},{"given":"Vojin G.","family":"Oklobdzija","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"doi-asserted-by":"crossref","unstructured":"Oklobdzija, V.G., Zeydel, B., Dao, H.Q., Mathew, S., Krishnamurthy, R.: Energy-Delay Estimation for High-Performance Microprocessor VLSI Adders. In: Proceeding of the 16th Symposium on Computer Arithmetic (June 2003)","key":"46_CR1","DOI":"10.1109\/ARITH.2003.1207688"},{"key":"46_CR2","volume-title":"Logical Effort Designing Fast CMOS Circuits","author":"D. Harris","year":"1999","unstructured":"Harris, D., Sproull, R.F., Sutherland, I.E.: Logical Effort Designing Fast CMOS Circuits. Morgan Kaufmann Publishers, San Francisco (1999)"},{"unstructured":"Stojanovic, V., Markovic, D., Nikolic, B., Horowitz, M.A., Brodersen, R.W.: Energy-Delay Tradeoffs in Combinational Logic Using Gate Sizing and Supply Voltage Optimization. In: Proceedings of the 28th European Solid-State Circuits Conference, ESSCIRC 2002, Florence, Italy, September 24\u201326, pp. 211\u2013214 (2002)","key":"46_CR3"},{"doi-asserted-by":"crossref","unstructured":"Brodersen, R.W., Horowitz, M.A., Markovic, D., Nikolic, B., Stojanovic, V.: Methods for True Power Minimization. In: International Conference on Computer-Aided Design, ICCAD-2002, Digest of Technical Papers, San Jose, CA, November 10\u201314, pp. 35\u201342 (2002)","key":"46_CR4","DOI":"10.1145\/774572.774578"},{"doi-asserted-by":"crossref","unstructured":"Zyuban, V., Strenski, P.: Unified Methodology for Resolving Power-Performance Tradeoffs at the Microachitectural and Circuit Levels. In: IEEE Symposium on Low Power Electronics and Design (2002)","key":"46_CR5","DOI":"10.1109\/LPE.2002.146731"},{"doi-asserted-by":"crossref","unstructured":"Zyuban, V.V., Kogge, P.M.: Inherently Lower-Power High-Performance Superscalar Architectures. In: IEEE Symposium on Low Power Electronics and Desing (2001)","key":"46_CR6","DOI":"10.1109\/12.910816"},{"doi-asserted-by":"crossref","unstructured":"Dao, H., Oklobdzija, V.G.: Performance Comparison of VLSI Adders Using Logical Effort. In: 12th International Workshop on Power And Timing Modeling,Optimization and Simulation, Sevilla, SPAIN, September 11\u201313 (2002)","key":"46_CR7","DOI":"10.1007\/3-540-45716-X_3"},{"issue":"8","key":"46_CR8","doi-asserted-by":"publisher","first-page":"786","DOI":"10.1109\/TC.1973.5009159","volume":"C-22","author":"P.M. Kogge","year":"1973","unstructured":"Kogge, P.M., Stone, H.S.: A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations. IEEE Trans. Computers\u00a0C-22(8), 786\u2013793 (1973)","journal-title":"IEEE Trans. Computers"},{"unstructured":"Han, T., Carlson, D.A., Levitan, S.P.: VLSI Design of High-Speed Low-Area Addition Circuitry. In: Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 418\u2013422 (1987)","key":"46_CR9"},{"key":"46_CR10","doi-asserted-by":"publisher","DOI":"10.1109\/9780470544846","volume-title":"High-Performance System Design: Circuits and Logic","author":"V.G. Oklobdzija","year":"1999","unstructured":"Oklobdzija, V.G.: High-Performance System Design: Circuits and Logic. IEEE Press, Los Alamitos (1999)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39762-5_46","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,31]],"date-time":"2019-05-31T12:58:50Z","timestamp":1559307530000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39762-5_46"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540200741","9783540397625"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39762-5_46","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}