{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,24]],"date-time":"2025-02-24T05:14:38Z","timestamp":1740374078465,"version":"3.37.3"},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540200741"},{"type":"electronic","value":"9783540397625"}],"license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39762-5_5","type":"book-chapter","created":{"date-parts":[[2010,7,22]],"date-time":"2010-07-22T23:08:02Z","timestamp":1279840082000},"page":"31-40","source":"Crossref","is-referenced-by-count":0,"title":["State Encoding for Low-Power FSMs in FPGA"],"prefix":"10.1007","author":[{"given":"Luis","family":"Mengibar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luis","family":"Entrena","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael G","family":"Lorenz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ra\u00fal","family":"S\u00e1nchez-Reillo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"5_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"459","DOI":"10.1007\/3-540-45716-X_36","volume-title":"Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation","author":"G. Sutter","year":"2002","unstructured":"Sutter, G., Teodorovich, E., L\u00f3pez-Buedo, S., Boemo, E.: Low-Power FSMs in FPGA: Encoding Alternatives. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds.) PATMOS 2002. LNCS, vol.\u00a02451, pp. 459\u2013467. Springer, Heidelberg (2002)"},{"key":"5_CR2","unstructured":"FPGA Compiler II \/ FPGA Express VHDL Reference Manual v. 1999.05. Synopsys Inc. (1999)"},{"key":"5_CR3","unstructured":"Xilinx Software Manual, Synthesis and Simulation Design Guide: Encoding State. Xilinx Inc. (2000)"},{"key":"5_CR4","doi-asserted-by":"crossref","unstructured":"Benini, L., De Micheli, G.: State Assignment for Low Power Dissipation. IEEE Journal of Solid State Circuits 30(3) (March 1995)","DOI":"10.1109\/4.364440"},{"key":"5_CR5","doi-asserted-by":"crossref","unstructured":"Tsui, C.-Y., Pedram, M., Despain, A.: Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. In: Proc. Design Automation Conf., pp. 18\u201323 (1994)","DOI":"10.1145\/196244.196255"},{"issue":"9","key":"5_CR6","doi-asserted-by":"publisher","first-page":"905","DOI":"10.1109\/43.59068","volume":"9","author":"T. Villa","year":"1990","unstructured":"Villa, T., Sangiovanni-Vincentelli, A.: NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Optimizations. IEEE Transactions on computer Aided Design\u00a09(9), 905\u2013924 (1990)","journal-title":"IEEE Transactions on computer Aided Design"},{"key":"5_CR7","doi-asserted-by":"crossref","unstructured":"Devadas, S., Ma, H., Newton, A.R., Sangiovanni-Vincentelli, A.: MUSTANG: State Assignment of Finite State MachinesTargeting Multi level Logic Implementations. IEEE Transactions on Computer Aided Design\u00a07(12) (December 1990)","DOI":"10.1109\/43.16807"},{"key":"5_CR8","unstructured":"Lin, B., Newton, A.R.: Synthesis of Multiple Level Logic from Simbolic High-Level Description Languages. In: Proc. of International Conf. VLSI, Agosto 1996, pp. 187\u2013196 (1996)"},{"key":"5_CR9","doi-asserted-by":"crossref","unstructured":"Chen, D.-S., Sharrafzadeh, M., Yeap, G.: State Encoding of Finite State Machines for Low Power Design. In: IEEE International Symposium on Circuits and Systems ISCAS 1995, vol.\u00a03, pp. 2309\u20132312 (1995)","DOI":"10.1109\/ISCAS.1995.523891"},{"key":"5_CR10","doi-asserted-by":"crossref","unstructured":"N\u00f6th, W., Kolla, R.: Spanning Tree Based State Encodin for low power Dissipation. In: Proc. Design Aut. and Test in Europe DATE 1999, March 1999, pp. 168\u2013174 (1999)","DOI":"10.1145\/307418.307482"},{"issue":"5","key":"5_CR11","doi-asserted-by":"publisher","first-page":"271","DOI":"10.1049\/ip-cds:20000671","volume":"147","author":"X. Wu","year":"2000","unstructured":"Wu, X., Pedram, M., Wang, L.: Multi-code state assignment for low power design. IEEE Proc. Circuits, Devices and Systems\u00a0147(5), 271\u2013275 (2000)","journal-title":"IEEE Proc. Circuits, Devices and Systems"},{"key":"5_CR12","unstructured":"Mart\u00ednez, M., Avedillo, M.J., Quintana, J.M., Huertas, J.L.: A flexible state assignment algorithm for low power implementations. In: Proc. Design of Circuits and Integrated Systems Conf., November 2001, pp. 154\u2013159 (2001)"},{"key":"5_CR13","doi-asserted-by":"crossref","unstructured":"Koegst, M., Franke, G., Rulke, S.T., Feske, K.: A strategy for low power FSM-Design Using multicriteria approach. In: PATMOS 1997, pp. 323\u2013329 (1997)","DOI":"10.1109\/EURMIC.1997.617303"},{"key":"5_CR14","unstructured":"McElvain, K.: LGSynth93 Benchmark Set: Version 4.0 (1993)"},{"key":"5_CR15","unstructured":"Sentovich, E., Singh, K., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Stephan, P., Brayton, R., Sangiovanni-Vincentelli, A.: SIS: A System for Sequential Circuit Synthesis. Tech. Report Mem. No UCB\/ERL M92\/41, Univ. California Berkeley (1992)"},{"key":"5_CR16","unstructured":"Modelsim SE\/EE Plus 5.4E. User\u2018s manual, V. 5.4. Model Technology Incorporated (August 2000)"},{"key":"5_CR17","unstructured":"Xilinx Foundation 4.1i tools, http:\/\/www.xilinx.com\/support\/library.htm"},{"key":"5_CR18","unstructured":"Xpower, Xpower Tutorial FPGA Design, Xpower (V1.0), Xilinx Inc (May 11, 2001)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39762-5_5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,23]],"date-time":"2025-02-23T07:36:06Z","timestamp":1740296166000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39762-5_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540200741","9783540397625"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39762-5_5","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}