{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,24]],"date-time":"2025-02-24T05:14:46Z","timestamp":1740374086402,"version":"3.37.3"},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540200741"},{"type":"electronic","value":"9783540397625"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39762-5_51","type":"book-chapter","created":{"date-parts":[[2010,7,22]],"date-time":"2010-07-22T23:08:02Z","timestamp":1279840082000},"page":"451-460","source":"Crossref","is-referenced-by-count":0,"title":["Metric Definition for Circuit Speed Optimization"],"prefix":"10.1007","author":[{"given":"X.","family":"Michel","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Verle","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Az\u00e9mard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Maurine","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Auvergne","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"2","key":"51_CR1","doi-asserted-by":"publisher","first-page":"400","DOI":"10.1109\/4.1000","volume":"23","author":"J.M. Shyu","year":"1988","unstructured":"Shyu, J.M., Sangiovanni-Vincentelli, A., Fishburn, J., Dunlop, A.: Optimization-based transistor sizing. IEEE J. Solid State Circuits\u00a023(2), 400\u2013409 (1988)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"9","key":"51_CR2","doi-asserted-by":"publisher","first-page":"1265","DOI":"10.1109\/4.84943","volume":"26","author":"S.R. Vemuru","year":"1991","unstructured":"Vemuru, S.R., Thorbjornsen, A.R., Tuszynski, A.A.: CMOS tapered buffer. IEEE J. Solid State Circuits\u00a026(9), 1265\u20131269 (1991)","journal-title":"IEEE J. Solid State Circuits"},{"key":"51_CR3","doi-asserted-by":"crossref","unstructured":"Paulin, P.G., Poirot, F.J.: Logic decomposition algorithm for the timing optimization of multilevel logic. In: Proc. ICCD 1989, pp. 329\u2013333 (1989)","DOI":"10.1109\/ICCD.1989.63382"},{"key":"51_CR4","doi-asserted-by":"crossref","unstructured":"Chan, P.K.: Algorithms for library-specific sizing of combinational logic. In: Proc. ACM\/IEEE Design Automation Conf., pp. 353-356 (1990)","DOI":"10.1145\/123186.123302"},{"key":"51_CR5","unstructured":"Fishburn, J., Dunlop, A.: TILOS: a posynomial programming approach to transistor sizing. In: Proc. Design Automation Conf., pp. 326\u2013328 (1985)"},{"key":"51_CR6","volume-title":"Logical Effort: Designing Fast CMOS Circuits","author":"I. Sutherland","year":"1999","unstructured":"Sutherland, I., Sproull, B., Harris, D.: Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann Publishers, Inc., San Francisco (1999)"},{"issue":"4","key":"51_CR7","doi-asserted-by":"publisher","first-page":"773","DOI":"10.1109\/JSSC.1982.1051810","volume":"SC17","author":"C. Mead","year":"1982","unstructured":"Mead, C., Rem, M.: Minimum propagation delays in VLSI. IEEE J. Solid State Circuits\u00a0SC17(4), 773\u2013775 (1982)","journal-title":"IEEE J. Solid State Circuits"},{"issue":"11","key":"51_CR8","doi-asserted-by":"publisher","first-page":"1352","DOI":"10.1109\/TCAD.2002.804088","volume":"21","author":"P. Maurine","year":"2002","unstructured":"Maurine, P., Rezzoug, M., Azemard, N., Auvergne, D.: Transition time modeling in deep submicron CMOS. IEEE trans. on Computer Aided Design\u00a021(11), 1352\u20131363 (2002)","journal-title":"IEEE trans. on Computer Aided Design"},{"key":"51_CR9","doi-asserted-by":"publisher","first-page":"646","DOI":"10.1109\/4.293109","volume":"29","author":"K.O. Jeppson","year":"1994","unstructured":"Jeppson, K.O.: Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay. IEEE J. Solid State Circuits\u00a029, 646\u2013654 (1994)","journal-title":"IEEE J. Solid State Circuits"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39762-5_51","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,23]],"date-time":"2025-02-23T07:35:24Z","timestamp":1740296124000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39762-5_51"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540200741","9783540397625"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39762-5_51","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}