{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,16]],"date-time":"2025-04-16T06:14:45Z","timestamp":1744784085491},"publisher-location":"Berlin, Heidelberg","reference-count":24,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540200741"},{"type":"electronic","value":"9783540397625"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39762-5_52","type":"book-chapter","created":{"date-parts":[[2010,7,22]],"date-time":"2010-07-22T19:08:02Z","timestamp":1279825682000},"page":"461-470","source":"Crossref","is-referenced-by-count":3,"title":["Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies"],"prefix":"10.1007","author":[{"given":"G.","family":"Tosik","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Gaffiot","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Z.","family":"Lisik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"I.","family":"O\u2019Connor","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Tissafi-Drissi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"52_CR1","unstructured":"International Technology Roadmap of Semiconductor 2001 Edition, http:\/\/public.itrs.net\/"},{"key":"52_CR2","unstructured":"Azar, K.: The History of Power Dissipation. Electronics Cooling\u00a06(1) (2000)"},{"issue":"9","key":"52_CR3","doi-asserted-by":"publisher","first-page":"965","DOI":"10.1109\/43.658565","volume":"16","author":"A. Vittal","year":"1997","unstructured":"Vittal, A., Marek-Sadowska, M.: Low Power Buffered Clock Tree Design. IEEE Trans. Comp. Aided Design and Integrated Circuits and Systems\u00a016(9), 965\u2013975 (1997)","journal-title":"IEEE Trans. Comp. Aided Design and Integrated Circuits and Systems"},{"issue":"6","key":"52_CR4","doi-asserted-by":"publisher","first-page":"663","DOI":"10.1109\/4.293111","volume":"29","author":"D. Liu","year":"1994","unstructured":"Liu, D., Svensson, C.: Power Consumption Estimation in CMOS VLSI Circuit. IEEE J. Solid-State Circuits\u00a029(6), 663\u2013670 (1994)","journal-title":"IEEE J. Solid-State Circuits"},{"key":"52_CR5","volume-title":"Clock Distribution Networks in VLSI Circuits and Systems","author":"E. Friedman","year":"1995","unstructured":"Friedman, E.: Clock Distribution Networks in VLSI Circuits and Systems. IEEE, N.Y (1995)"},{"issue":"9","key":"52_CR6","doi-asserted-by":"publisher","first-page":"562","DOI":"10.1049\/el:19880382","volume":"24","author":"C. Svensson","year":"1988","unstructured":"Svensson, C., Afghahi, M.: On RC Line Delays and Scaling in VLSI Systems. IEE Elect. Letters\u00a024(9), 562\u2013563 (1988)","journal-title":"IEE Elect. Letters"},{"key":"52_CR7","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/55.144942","volume":"13","author":"J.H. Chern","year":"1992","unstructured":"Chern, J.H., Huang, J., Arledge, L., Li, P.C., Yang, P.: Multilevel Metal Capacitance Models for CAD Design Synthesis Systems. IEEE Elect. Device Lett.\u00a013, 32 (1992)","journal-title":"IEEE Elect. Device Lett."},{"key":"52_CR8","unstructured":"Grover, F.: Inductance Calculations Working Formulas and Tables, Instrum. Soc. of America (1945)"},{"key":"52_CR9","volume-title":"Circuits, Interconnections, and Packaging for VLSI","author":"H.B. Bakoglu","year":"1990","unstructured":"Bakoglu, H.B.: Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Reading (1990)"},{"key":"52_CR10","doi-asserted-by":"crossref","unstructured":"Amann, M.C., Ortsiefer, M., Shau, R.: Surface-Emitting Laser Diodes for Telecommunications. In: SODC 2002, Stuttgart, Germany, March 10-16 (2002)","DOI":"10.1117\/12.460475"},{"issue":"4","key":"52_CR11","doi-asserted-by":"publisher","first-page":"383","DOI":"10.1143\/JJAP.40.L383","volume":"40","author":"A. Sakai","year":"2001","unstructured":"Sakai, A., Hara, G., Baba, T.: Propagation Characteristics of Ultrahigh-D Optical Waveguides on Silicon-on-Isulator Substrate. Jpn. J. Applied Physics\u00a040(4), 383\u2013385 (2001)","journal-title":"Jpn. J. Applied Physics"},{"issue":"4","key":"52_CR12","doi-asserted-by":"publisher","first-page":"1174","DOI":"10.1109\/50.301810","volume":"12","author":"J.J. Morikuni","year":"1994","unstructured":"Morikuni, J.J., Dharchoudhury, A., Leblebici, Y., Kang, S.M.: Improvements to the Standard Theory for Photoreceivers Noise. J. Lightwave Techn.\u00a012(4), 1174\u20131184 (1994)","journal-title":"J. Lightwave Techn."},{"key":"52_CR13","unstructured":"O\u2019Connor, I., Mieyeville, F., Tissafi-Drissi, F., Gaffiot, F.: Exploration Parametrique d\u2019Amplificateurs de Transimpedance CMOS a Bande Passante Maximisee. In: TAISA 2002., pp. 73\u201376 (2002)"},{"key":"52_CR14","doi-asserted-by":"crossref","first-page":"3187","DOI":"10.1002\/j.1538-7305.1969.tb01742.x","volume":"48","author":"D. Marcuse","year":"1969","unstructured":"Marcuse, D.: Mode Conversion Caused by Surface Imperfections of a Dielectric Slab Waveguide. Bell System Technical J.\u00a048, 3187\u20133214 (1969)","journal-title":"Bell System Technical J."},{"key":"52_CR15","doi-asserted-by":"publisher","first-page":"977","DOI":"10.1007\/BF00708339","volume":"26","author":"F.P. Payne","year":"1994","unstructured":"Payne, F.P., Lacey, J.P.R.: A Theoretical Analysis of Scattering Loss from Planar Optical Waveguide. Optical and Quantum Electronics\u00a026, 977\u2013986 (1994)","journal-title":"Optical and Quantum Electronics"},{"key":"52_CR16","volume-title":"Electro-Optics Handbook","author":"H. Nishihara","year":"2000","unstructured":"Nishihara, H., Haruna, M., Suhara, T.: Electro-Optics Handbook. McGraw Hill, New York (2000)"},{"issue":"6","key":"52_CR17","doi-asserted-by":"publisher","first-page":"296","DOI":"10.1049\/el:19860202","volume":"22","author":"C.M. Kim","year":"1986","unstructured":"Kim, C.M., Jung, B.G., Lee, C.W.: Analysis of Dielectric Rectangular Waveguide by Modified Effective-Index Method. Electron. Letters\u00a022(6), 296\u2013298 (1986)","journal-title":"Electron. Letters"},{"key":"52_CR18","doi-asserted-by":"crossref","unstructured":"Lee, K.K., Lim, D.R., Kimerling, L.C.: Fabrication of Ultralow-Loss Si\/SiO2 Waveguides by Roughness Reduction. Optical Letters\u00a026(23) (2001)","DOI":"10.1364\/OL.26.001888"},{"key":"52_CR19","unstructured":"Marcuse, D.: Light Transmission Optics, New York, Van Nostrand Reinhold (1973)"},{"issue":"5","key":"52_CR20","doi-asserted-by":"publisher","first-page":"309","DOI":"10.1364\/OL.16.000309","volume":"16","author":"F.S. Chu","year":"1992","unstructured":"Chu, F.S., Liu, P.L.: Low-Loss Coherent-Coupling Y-Branches. Optics Lett.\u00a016(5), 309\u2013311 (1992)","journal-title":"Optics Lett."},{"issue":"5","key":"52_CR21","doi-asserted-by":"publisher","first-page":"753","DOI":"10.1109\/50.19110","volume":"7","author":"M. Rangaraj","year":"1989","unstructured":"Rangaraj, M., Minakata, M., Kawakami, S.: Low Loss Integrated Optical Y-Branch. J. Lightwave Technol.\u00a07(5), 753\u2013758 (1989)","journal-title":"J. Lightwave Technol."},{"key":"52_CR22","doi-asserted-by":"crossref","unstructured":"Sakai, A., Fukazawa, T.: Low Loss Ultra-Small Branches in a Silicon Photonic Wire Waveguide. IEICE Trans. Electron\u00a0E85-C(4) (2002)","DOI":"10.1364\/IPR.2002.IThI12"},{"key":"52_CR23","doi-asserted-by":"publisher","first-page":"1223","DOI":"10.1364\/AO.39.001223","volume":"39","author":"S.M. Schultz","year":"2000","unstructured":"Schultz, S.M., Glytsis, E.N., Gaylord, T.K.: Design, Fabrication, and Performance of Preferential-Order Volume Grating Waveguide Couplers. Appl. Opt.\u00a039, 1223 (2000)","journal-title":"Appl. Opt."},{"key":"52_CR24","unstructured":"http:\/\/www-device.eecs.berkeley.edu"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39762-5_52","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,31]],"date-time":"2019-05-31T08:58:26Z","timestamp":1559293106000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39762-5_52"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540200741","9783540397625"],"references-count":24,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39762-5_52","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}