{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,2]],"date-time":"2025-03-02T05:44:25Z","timestamp":1740894265808,"version":"3.38.0"},"publisher-location":"Berlin, Heidelberg","reference-count":30,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540201229"},{"type":"electronic","value":"9783540398646"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39864-6_25","type":"book-chapter","created":{"date-parts":[[2011,1,7]],"date-time":"2011-01-07T01:42:19Z","timestamp":1294364539000},"page":"305-319","source":"Crossref","is-referenced-by-count":2,"title":["L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy"],"prefix":"10.1007","author":[{"given":"Philip","family":"Machanick","sequence":"first","affiliation":[]},{"given":"Zunaid","family":"Patel","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"25_CR1","doi-asserted-by":"crossref","unstructured":"Alexander, T., Kedem, G.: Distributed prefetch-buffer\/cache design for high-performance memory systems. In: Proc. 2nd IEEE Symp. on High- Performance Computer Architecture, San Jose, CA, February 1996, pp. 254\u2013263 (1996)","DOI":"10.1109\/HPCA.1996.501191"},{"key":"25_CR2","unstructured":"AMD. HyperTransport technology: Simplifying system design [online] (October 2002), http:\/\/www.hypertransport.org\/docs\/26635A_HT_System_Design.pdf"},{"issue":"6","key":"25_CR3","doi-asserted-by":"publisher","first-page":"885","DOI":"10.1147\/rd.446.0885","volume":"44","author":"J.M. Borkenhagen","year":"2000","unstructured":"Borkenhagen, J.M., Eickemeyer, R.J., Kalla, R.N., Kunkel, S.R.: A multithreaded PowerPC processor for commercial servers. IBM J. Research and Development\u00a044(6), 885\u2013898 (2000)","journal-title":"IBM J. Research and Development"},{"key":"25_CR4","doi-asserted-by":"crossref","unstructured":"Chen, T., Baer, J.: Reducing memory latency via non-blocking and prefetching caches. In: Proc. 5th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-5), September 1992, pp. 51\u201361 (1992)","DOI":"10.1145\/143365.143486"},{"key":"25_CR5","doi-asserted-by":"crossref","unstructured":"Chen, T.-F.: An effective programmable prefetch engine for on-chip caches. In: Proc. 28th Int. Symp. on Microarchitecture (MICRO-28), Ann Arbor, MI, November 29 \u2013 December 1, pp. 237\u2013242 (1995)","DOI":"10.1109\/MICRO.1995.476831"},{"key":"25_CR6","doi-asserted-by":"crossref","unstructured":"Cheriton, D.R., Goosen, H.A., Holbrook, H., Machanick, P.: Restructuring a parallel simulation to improve cache behavior in a shared-memory multiprocessor: The value of distributed synchronization. In: Proc. 7th Workshop on Parallel and Distributed Simulation, San Diego, May 1993, pp. 159\u2013162 (1993)","DOI":"10.1145\/158459.158480"},{"key":"25_CR7","doi-asserted-by":"crossref","unstructured":"Cheriton, D.R., Slavenburg, G., Boyle, P.: Software-controlled caches in the VMP multiprocessor. In: Proc. 13th Int. Symp. on Computer Architecture (ISCA 1986), Tokyo, June 1986, pp. 366\u2013374 (1986)","DOI":"10.21236\/ADA221699"},{"issue":"6","key":"25_CR8","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/40.641593","volume":"17","author":"R. Crisp","year":"1997","unstructured":"Crisp, R.: Direct Rambus technology: The new main memory standard. IEEE Micro\u00a017(6), 18\u201328 (1997)","journal-title":"IEEE Micro"},{"key":"25_CR9","unstructured":"Davis, B., Mudge, T., Jacob, B., Cuppu, V.: DDR2 and low latency variants. In: Solving the Memory Wall Problem Workshop, Vancouver, Canada (June 2000); in conjunction with 26th Annual lnt. Symp. on Computer Architecture"},{"key":"25_CR10","doi-asserted-by":"crossref","unstructured":"Hallnor, E.G., Reinhardt, S.K.: A fully associative software-managed cache design. In: Proc. 27th Annual Int. Symp. on Computer Architecture, Vancouver, BC, pp. 107\u2013116 (2000)","DOI":"10.1145\/339647.339660"},{"key":"25_CR11","volume-title":"The Cache Memory Book","author":"J. Handy","year":"1998","unstructured":"Handy, J.: The Cache Memory Book, 2nd edn. Academic Press, San Diego (1998)","edition":"2"},{"key":"25_CR12","volume-title":"Computer Architecture: A Quantitative Approach","author":"J.L. Hennessy","year":"1996","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 2nd edn. Morgan Kaufmann, San Francisco (1996)","edition":"2"},{"key":"25_CR13","doi-asserted-by":"crossref","unstructured":"Huck, J., Hays, J.: Architectural support for translation table management in large address space machines. In: Proc. 20th Int. Symp. on Computer Architecture (ISCA 1993), San Diego, CA, May 1993, pp. 39\u201350 (1993)","DOI":"10.1145\/165123.165128"},{"key":"25_CR14","doi-asserted-by":"crossref","unstructured":"Jacob, B., Mudge, T.: Software-managed address translation. In: Proc. Third Int. Symp. on High-Performance Computer Architecture, San Antonio, TX, February 1997, pp. 156\u2013167 (1997)","DOI":"10.1109\/HPCA.1997.569652"},{"key":"25_CR15","doi-asserted-by":"crossref","unstructured":"Jacob, B.L., Mudge, T.N.: A look at several memory management units, TLB-refill mechanisms, and page table organizations. In: Proc. 8th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, CA, pp. 295\u2013306 (1998)","DOI":"10.1145\/291069.291065"},{"issue":"4","key":"25_CR16","doi-asserted-by":"publisher","first-page":"7","DOI":"10.1145\/218864.218866","volume":"23","author":"E.E. Johnson","year":"1995","unstructured":"Johnson, E.E.: Graffiti on the memory wall. Computer Architecture News\u00a023(4), 7\u20138 (1995)","journal-title":"Computer Architecture News"},{"key":"25_CR17","doi-asserted-by":"crossref","unstructured":"Jouppi, N.P.: Cache write policies and performance. In: Proc. 20th annual Int. Symp. on Computer Architecture, San Diego, CA, pp. 191\u2013201 (1993)","DOI":"10.1145\/173682.165154"},{"key":"25_CR18","unstructured":"Lee, J.-S., Hong, W.-K., Kim, S.-D.: Design and evaluation of a selective compressed memory system. In: Proc. IEEE Int. Conf. on Computer Design, Austin, TX, October 10-13, pp. 184\u2013191 (1999)"},{"issue":"3","key":"25_CR19","doi-asserted-by":"publisher","first-page":"322","DOI":"10.1145\/263326.263382","volume":"15","author":"J.L. Lo","year":"1997","unstructured":"Lo, J.L., Emer, J.S., Levy, H.M., Stamm, R.L., Tullsen, D.M.: Converting threadlevel parallelism to instruction-level parallelism via simultaneous multithreading. ACM Trans. on Computer Systems\u00a015(3), 322\u2013354 (1997)","journal-title":"ACM Trans. on Computer Systems"},{"issue":"5","key":"25_CR20","doi-asserted-by":"publisher","first-page":"23","DOI":"10.1145\/242694.242709","volume":"24","author":"P. Machanick","year":"1996","unstructured":"Machanick, P.: The case for SRAM main memory. Computer Architecture News\u00a024(5), 23\u201330 (1996)","journal-title":"Computer Architecture News"},{"key":"25_CR21","first-page":"68","volume":"25","author":"P. Machanick","year":"2000","unstructured":"Machanick, P.: Scalability of the RAMpage memory hierarchy. South African Computer Journal\u00a0(25), 68\u201373 (2000)","journal-title":"South African Computer Journal"},{"key":"25_CR22","doi-asserted-by":"crossref","unstructured":"Machanick, P., Salverda, P., Pompe, L.: Hardware-software trade-offs in a Direct Rambus implementation of the RAMpage memory hierarchy. In: Proc. 8th Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, CA, October 1998, pp. 105\u2013114 (1998)","DOI":"10.1145\/291069.291032"},{"key":"25_CR23","unstructured":"Machanick, P.: An Object-Oriented Library for Shared-Memory Parallel Simulations. PhD Thesis, Dept. of Computer Science, University of Cape Town (1996)"},{"issue":"6","key":"25_CR24","first-page":"16","volume":"30","author":"P. Machanick","year":"2002","unstructured":"Machanick, P.: What if DRAM is a slow peripheral? Computer Architecture News\u00a030(6), 16\u201319 (2002)","journal-title":"Computer Architecture News"},{"key":"25_CR25","doi-asserted-by":"crossref","unstructured":"Mowry, T.C., Lam, M.S., Gupta, A.: Design and evaluation of a compiler algorithm for prefetching. In: Proc. 5th Int. Conf. on Architectural Support for Programming Languages and Operating Systems, September 1992, pp. 62\u201373 (1992)","DOI":"10.1145\/143365.143488"},{"issue":"4","key":"25_CR26","doi-asserted-by":"publisher","first-page":"34","DOI":"10.1109\/88.473612","volume":"3","author":"M. Rosenblum","year":"1995","unstructured":"Rosenblum, M., Herrod, S.A., Witchel, E., Gupta, A.: Complete computer system simulation: The SimOS approach. IEEE Parallel and Distributed Technology\u00a03(4), 34\u201343 (1995)","journal-title":"IEEE Parallel and Distributed Technology"},{"key":"25_CR27","doi-asserted-by":"crossref","unstructured":"Saulsbury, A., Pong, F., Nowatzyk, A.: Missing the memory wall: the case for processor\/memory integration. In: Proc. 23rd annual Int. Symp. on Computer architecture, Philadelphia, PA, pp. 90\u2013101 (1996)","DOI":"10.1145\/232974.232984"},{"key":"25_CR28","doi-asserted-by":"crossref","unstructured":"Sprangle, E., Carmean, D.: Increasing processor performance by implementing deeper pipelines. In: Proc. 29th Annual Int. Symp. on Computer architecture, Anchorage, Alaska, pp. 25\u201334 (2002)","DOI":"10.1109\/ISCA.2002.1003559"},{"issue":"1","key":"25_CR29","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1147\/rd.461.0005","volume":"46","author":"J.M. Tendler","year":"2002","unstructured":"Tendler, J.M., Dodson Jr., J.S., Fields, J.S., Le, H., Sinharoy, B.: POWER4 system microarchitecture. IBM J. Research and Development\u00a046(1), 5\u201325 (2002)","journal-title":"IBM J. Research and Development"},{"issue":"1","key":"25_CR30","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1145\/216585.216588","volume":"23","author":"W.A. Wulf","year":"1995","unstructured":"Wulf, W.A., McKee, S.A.: Hitting the memory wall: Implications of the obvious. Computer Architecture News\u00a023(1), 20\u201324 (1995)","journal-title":"Computer Architecture News"}],"container-title":["Lecture Notes in Computer Science","Advances in Computer Systems Architecture"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39864-6_25","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T13:41:37Z","timestamp":1740836497000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39864-6_25"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540201229","9783540398646"],"references-count":30,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39864-6_25","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}