{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T22:11:45Z","timestamp":1725574305715},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540201229"},{"type":"electronic","value":"9783540398646"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-39864-6_6","type":"book-chapter","created":{"date-parts":[[2011,1,7]],"date-time":"2011-01-07T01:42:19Z","timestamp":1294364539000},"page":"54-68","source":"Crossref","is-referenced-by-count":0,"title":["Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA"],"prefix":"10.1007","author":[{"given":"Kiyoshi","family":"Oguri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuichiro","family":"Shibata","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akira","family":"Nagoya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"6_CR1","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"323","DOI":"10.1007\/BFb0057634","volume-title":"Evolvable Systems: From Biology to Hardware","author":"K. Oguri","year":"1998","unstructured":"Oguri, K., Imlig, N., Ito, H., Nagami, K., Konishi, R., Shiozawa, T.: General purpose computer architecture based on fully programmable logic. In: Sipper, M., Mange, D., P\u00e9rez-Uribe, A. (eds.) ICES 1998. LNCS, vol.\u00a01478, pp. 323\u2013334. Springer, Heidelberg (1998)"},{"issue":"9","key":"6_CR2","first-page":"1431","volume":"E81-C","author":"K. Nagami","year":"1998","unstructured":"Nagami, K., Oguri, K., Shiozawa, T., Ito, H., Konishi, R.: Plastic cell architecture: A scalable device architecture for general-purpose reconfigurable computing. IEICE Trans. Electron\u00a0E81-C(9), 1431\u20131437 (1998)","journal-title":"IEICE Trans. Electron"},{"issue":"12","key":"6_CR3","first-page":"2409","volume":"E83-A","author":"N. Imlig","year":"2000","unstructured":"Imlig, N., Shiozawa, T., Konishi, R., Oguri, K., Nagami, K., Ito, H., Inamori, M., Nakada, H.: Programmable dataflow computing on PCA. IEICE Trans. Fundamentals\u00a0E83-A(12), 2409\u20132416 (2000)","journal-title":"IEICE Trans. Fundamentals"},{"key":"6_CR4","doi-asserted-by":"crossref","unstructured":"Sahni, M., Nanya, T.: On the CSC property of signal transition graph specifications for asynchronous circuit design. In: Proc. ASP-DAC, February 1998, pp. 183\u2013189 (1998)","DOI":"10.1109\/ASPDAC.1998.669440"},{"key":"6_CR5","unstructured":"Nanya, T.: Asynchronous microprocessor architecture and design. In: Proc. FED-PDI Joint Conference on 21th-Century Electron Devices (FPC 1998) (June 1998)"},{"issue":"4","key":"6_CR6","doi-asserted-by":"publisher","first-page":"385","DOI":"10.1109\/12.588033","volume":"46","author":"J.V. Woods","year":"1997","unstructured":"Woods, J.V., Day, P., Furber, S.B., Garside, J.D., Paver, N.C., Temple, S.: AMULET1: An asynchronous ARM microprocessor. IEEE Trans. Comput.\u00a046(4), 385\u2013398 (1997)","journal-title":"IEEE Trans. Comput."},{"key":"6_CR7","doi-asserted-by":"crossref","unstructured":"Konishi, R., Ito, H., Nakada, H., Nagoya, A., Oguri, K., Imlig, N., Shiozawa, T., Inamori, M., Nagami, K.: PCA-1: A fully asynchronous, self-reconfigurable LSI. In: Proc. 7th Int. Symposium on Asynchronous Circuit and Systems (ASYNC 2001), March 2001, pp. 54\u201361 (2001)","DOI":"10.1109\/ASYNC.2001.914069"},{"key":"6_CR8","doi-asserted-by":"crossref","unstructured":"Ito, H., Konishi, R., Nakada, H., Oguri, K., Nagoya, A., Imlig, N., Nagami, K., Shiozawa, T., Inamori, M.: Dynamically reconfigurable logic LSI \u2014 PCA-1. In: Proc. 2001 Symposium on VLSI Circuits, June 2001, pp. 103\u2013106 (2001)","DOI":"10.1109\/VLSIC.2001.934208"},{"issue":"4","key":"6_CR9","first-page":"804","volume":"E00-A","author":"M. Inamori","year":"2002","unstructured":"Inamori, M., Nakada, H., Konishi, R., Nagoya, A., Oguri, K.: A method of mapping finite state machine into PCA plastic parts. IEICE Trans. Fundamentals\u00a0E00-A(4), 804\u2013810 (2002)","journal-title":"IEICE Trans. Fundamentals"},{"key":"6_CR10","unstructured":"Seitz, C.L.: System Timing. in C. Mead and L. Conway: Introduction to VLSI Systems, pp. 218\u2013262. Addison-Wesley, Reading (1980) ISBN 0-201-04358-0"},{"key":"6_CR11","volume-title":"Asynchronous Sequential Switching Circuits","author":"S.H. Unger","year":"1969","unstructured":"Unger, S.H.: Asynchronous Sequential Switching Circuits. John Wiley & Sons, Chichester (1969)"},{"issue":"6","key":"6_CR12","doi-asserted-by":"publisher","first-page":"720","DOI":"10.1145\/63526.63532","volume":"32","author":"I.E. Sutherland","year":"1989","unstructured":"Sutherland, I.E.: Micropipelines. Commun. ACM\u00a032(6), 720\u2013738 (1989)","journal-title":"Commun. ACM"},{"key":"6_CR13","unstructured":"Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Trans. Inf. & Syst.\u00a0E80-D(3) (March 1997)"},{"issue":"1","key":"6_CR14","doi-asserted-by":"publisher","first-page":"2","DOI":"10.1109\/12.123377","volume":"41","author":"David","year":"1992","unstructured":"David, Ginosar, R., Yoeli, M.: An efficient implementation of boolean function as self-timed circuits. IEEE Trans. Comput.\u00a041(1), 2\u201311 (1992)","journal-title":"IEEE Trans. Comput."},{"key":"6_CR15","doi-asserted-by":"crossref","unstructured":"Meng, T.H.: Synchronization Design for Digital Systems. Kluwer Academic Publishers, Dordrecht (1991) ISBN 0-7923-9128-4","DOI":"10.1007\/978-1-4615-3990-2"},{"key":"6_CR16","doi-asserted-by":"crossref","unstructured":"Myers, C.J.: Asynchronous Circuit Design. John Wiley & Sons, Chichester (2001) ISBN 0-471-41543- X","DOI":"10.1002\/0471224146"},{"key":"6_CR17","unstructured":"Isshiki, T.: High-Performance Bit-Serial Datapath Implementation for Large-Scale Configurable Systems. Ph.D. Thesis, Tokyo Institute of Technology (April 1996)"},{"key":"6_CR18","unstructured":"Okuyama, Y., Kuroda, K.: Simulation framework for circuits on plastic cell architecture (PCA). IPSJ SIG Notes 2001-SLDM-101(42), 15\u201322 (May 2001)"},{"key":"6_CR19","volume-title":"Principles of CMOS VLSI Design: A System Perspective","author":"N. Weste","year":"1993","unstructured":"Weste, N., Eshraghian, K.: Principles of CMOS VLSI Design: A System Perspective, 2nd edn. Addison-Wesley, Reading (1993)","edition":"2"},{"issue":"8","key":"6_CR20","doi-asserted-by":"publisher","first-page":"972","DOI":"10.1109\/12.156540","volume":"41","author":"M.A. Hasan","year":"1992","unstructured":"Hasan, M.A., Bhargava, V.K.: Bit-serial systolic divider and multiplier for finite fields GF(2m). IEEE Trans. Comput.\u00a041(8), 972\u2013980 (1992)","journal-title":"IEEE Trans. Comput."}],"container-title":["Lecture Notes in Computer Science","Advances in Computer Systems Architecture"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-39864-6_6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,23]],"date-time":"2019-03-23T09:31:57Z","timestamp":1553333517000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-39864-6_6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540201229","9783540398646"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-39864-6_6","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]}}}