{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:13:39Z","timestamp":1763468019832,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":15,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540408222"},{"type":"electronic","value":"9783540452348"}],"license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-45234-8_120","type":"book-chapter","created":{"date-parts":[[2011,1,8]],"date-time":"2011-01-08T06:12:05Z","timestamp":1294467125000},"page":"1062-1066","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":87,"title":["FPGA Implementations of Neural Networks \u2013 A Survey of a Decade of Progress"],"prefix":"10.1007","author":[{"given":"Jihan","family":"Zhu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Peter","family":"Sutton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2003,9,30]]},"reference":[{"issue":"3","key":"120_CR1","doi-asserted-by":"publisher","first-page":"288","DOI":"10.1109\/4.121550","volume":"28","author":"C.E. Cox","year":"1992","unstructured":"Cox, C.E., Blanz, E.: GangLion - a fast field Programmable gate array implementation of a connectionist classifier. IEEE Journal of Solid-State Circuits\u00a028(3), 288\u2013299 (1992)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"120_CR2","doi-asserted-by":"crossref","unstructured":"Eldredge, J.G., Hutchings, B.L.: Density enhancement of a neural network using FPGAs and run-time reconfiguration. In: Proceedings of IEEE Workshop an Field-Programmable Custom Computing Machines, pp. 180\u2013188 (1994)","DOI":"10.1109\/FPGA.1994.315611"},{"key":"120_CR3","doi-asserted-by":"crossref","unstructured":"James-Roxby, P., Blodget, B.A.: Adapting constant multipliers in a neural network implementation. In: Proceedings of IEEE Symposium an Field-Programmable Custom Computing Machines, pp. 335\u2013336 (2000)","DOI":"10.1109\/FPGA.2000.903442"},{"key":"120_CR4","doi-asserted-by":"crossref","unstructured":"Zhu, J., Milne, G.J., Gunther, B.K.: Towards an FPGA based reconfigurable computing environment for neural network implementations. In: Proceedings of 9th International Conference an Artificial Neural Networks, vol.2, pp. 661-666 (1999)","DOI":"10.1049\/cp:19991186"},{"key":"120_CR5","doi-asserted-by":"publisher","first-page":"439","DOI":"10.1007\/3-540-60294-1_138","volume-title":"Proceedings of the 5th International Workshop an Field-Programmable Logic and Applications","author":"S.A. Guccione","year":"1995","unstructured":"Guccione, S.A., Gonzalez, M.: Classification and Performance ofreconfigurable architectures. In: Proceedings of the 5th International Workshop an Field-Programmable Logic and Applications, pp. 439\u2013448. Springer, Berlin (1995)"},{"key":"120_CR6","first-page":"382","volume-title":"Proceedings of the Sixth International Conference an Artificial Neural Networks","author":"A. Perez-Uribe","year":"1996","unstructured":"Perez-Uribe, A., Sanchez, E.: FPGA Implementation of an Adaptable-Size Neural Network. In: Proceedings of the Sixth International Conference an Artificial Neural Networks, pp. 382\u2013388. Springer, Heidelberg (1996)"},{"key":"120_CR7","doi-asserted-by":"crossref","unstructured":"de Garis, H., et al.: Initial evolvability experiments an the CAM-brain machines (CBMs). In: Proceedings of the, Congress an Evolutionary Computation, vol.2, pp. 635-641 (2001)","DOI":"10.1109\/CEC.2001.934451"},{"key":"120_CR8","doi-asserted-by":"publisher","first-page":"260","DOI":"10.1007\/3-540-44614-1_29","volume-title":"Proceedings of the 10th International Workshop an Field Programmable Logic and Applications - Roadmap to Reconfigurable Computing","author":"J. Zhu","year":"2000","unstructured":"Zhu, J., Milne, G.: Implementing Kak Neural Networks an a Reconfigurable Computing Pla form. In: Proceedings of the 10th International Workshop an Field Programmable Logic and Applications - Roadmap to Reconfigurable Computing, pp. 260\u2013269. Springer, Heidelberg (2000)"},{"issue":"1","key":"120_CR9","doi-asserted-by":"publisher","first-page":"53","DOI":"10.1109\/72.182695","volume":"4","author":"M. Marchesi","year":"1993","unstructured":"Marchesi, M., et al.: Fast neural Ntworks without multipliers. IEEE Transactions an Neural Networks\u00a04(1), 53\u201362 (1993)","journal-title":"IEEE Transactions an Neural Networks"},{"key":"120_CR10","unstructured":"Nichols, K., Moussa, M., Areibi, S.: Feasibility of Floating-Point Arithmetic in FPGA based Artificial Neural Networks. In: Proceedings of the 15th International Conference an Computer Applications in Industry and Engineering, San Diego, Califomia (2002)"},{"key":"120_CR11","doi-asserted-by":"crossref","unstructured":"Reyneri, L.M.: Theoretical and implementation aspects ofpulse streams: an overview. In: Proceedings of the 7th International Conference an Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, pp. 78\u201389 (1999)","DOI":"10.1109\/MN.1999.758849"},{"issue":"1045-9227","key":"120_CR12","doi-asserted-by":"publisher","first-page":"236","DOI":"10.1109\/TNN.2002.804312","volume":"14","author":"H. Hikawa","year":"2003","unstructured":"Hikawa, H.: A new digital pulse-mode neuron with adjustable activation function. IEEE Transactions an Neural Networks\u00a014(1045-9227), 236\u2013242 (2003)","journal-title":"IEEE Transactions an Neural Networks"},{"key":"120_CR13","doi-asserted-by":"crossref","unstructured":"Holt, J.L., Baker, T.E.: Back propagation simulations using limited precision calculations. In: Proceedings of International Joint Conference an Neural Networks, vol. 2, pp. 121\u2013126 (1991)","DOI":"10.1109\/IJCNN.1991.155324"},{"key":"120_CR14","doi-asserted-by":"publisher","first-page":"395","DOI":"10.1016\/S0893-6080(02)00032-1","volume":"15","author":"S. Draghici","year":"2002","unstructured":"Draghici, S.: On the capabilities of neural networks using limited precision weights. Neural Networks\u00a015, 395\u2013414 (2002)","journal-title":"Neural Networks"},{"key":"120_CR15","unstructured":"Wolf, D.F., Romero, R.A.F., Marques, E.: Using Embedded Processors in Hardware Models of Artificial Neural Networks. In: Proceedings of SBAI - Simp\u00f3sio Brasileiro de Automao Inteligente, pp. 78\u201383 (2001)"}],"container-title":["Lecture Notes in Computer Science","Field Programmable Logic and Application"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-45234-8_120","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T14:56:34Z","timestamp":1740840994000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-45234-8_120"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540408222","9783540452348"],"references-count":15,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-45234-8_120","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]},"assertion":[{"value":"30 September 2003","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}