{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,25]],"date-time":"2025-03-25T16:25:32Z","timestamp":1742919932065,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540408222"},{"type":"electronic","value":"9783540452348"}],"license":[{"start":{"date-parts":[[2003,1,1]],"date-time":"2003-01-01T00:00:00Z","timestamp":1041379200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1007\/978-3-540-45234-8_83","type":"book-chapter","created":{"date-parts":[[2011,1,8]],"date-time":"2011-01-08T06:12:05Z","timestamp":1294467125000},"page":"859-868","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":14,"title":["An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall"],"prefix":"10.1007","author":[{"given":"John W.","family":"Lockwood","sequence":"first","affiliation":[]},{"given":"Christopher","family":"Neely","sequence":"additional","affiliation":[]},{"given":"Christopher","family":"Zuver","sequence":"additional","affiliation":[]},{"given":"James","family":"Moscola","sequence":"additional","affiliation":[]},{"given":"Sarang","family":"Dharmapurikar","sequence":"additional","affiliation":[]},{"given":"David","family":"Lim","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2003,9,30]]},"reference":[{"key":"83_CR1","unstructured":"Franklin, R., Carver, D., Hutchings, B.L.: Assisting network intrusion detection with reconfigurable hardware. In: FCCM, Napa, CA (April 2002)"},{"key":"83_CR2","doi-asserted-by":"crossref","unstructured":"Lockwood, J.W.: Evolvable internet hardware platforms. In: The 3rd NASA\/DoD Workshop on Evolvable Hardware (EH 2001), July 2001, pp. 271\u2013279 (2001)","DOI":"10.1109\/EH.2001.937971"},{"key":"83_CR3","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"254","DOI":"10.1007\/3-540-44687-7_27","volume-title":"Field-Programmable Logic and Applications","author":"F. Braun","year":"2001","unstructured":"Braun, F., Lockwood, J., Waldvogel, M.: Reconfigurable router modules using network protocol wrappers. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol.\u00a02147, pp. 254\u2013263. Springer, Heidelberg (2001)"},{"key":"83_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"452","DOI":"10.1007\/3-540-46117-5_48","volume-title":"Field-Programmable Logic and Applications. Reconfigurable Computing Is Going Mainstream","author":"Y. Cho","year":"2002","unstructured":"Cho, Y., Nahab, S., Mangione-Smith, W.H.: Specialized hardware for deep network packet filtering. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol.\u00a02438, p. 452. Springer, Heidelberg (2002)"},{"key":"83_CR5","unstructured":"Moscola, J., Lockwood, J., Loui, R.P., Pachos, M.: Implementation of a contentscanning module for an Internet firewall. In: FCCM, Napa, CA (April 2003)"},{"key":"83_CR6","unstructured":"Brelet, J.-L.: Using block RAM for high performance read\/write CAMs. Xilinx XAPP204 (May 2002)"},{"key":"83_CR7","doi-asserted-by":"crossref","unstructured":"Duan, H., Lockwood, J.W., Kang, S.M., Will, J.: High-performance OC- 12\/OC-48 queue design prototype for input-buffered ATM switches. In: INFOCOM 1997, Kobe, Japan, April 1997, pp. 20\u201328 (1997)","DOI":"10.1109\/INFCOM.1997.635110"},{"key":"83_CR8","unstructured":"Dharmapurikar, S., Lockwood, J.: Synthesizable design of a multi-module memory controller. Washington University, Department of Computer Science, Technical Report WUCS-01-26 (October 2001)"},{"key":"83_CR9","unstructured":"Acceleration of Algorithms in Hardware (September 2001), http:\/\/www.arl.wustl.edu\/~lockwood\/class\/cs535\/"},{"key":"83_CR10","unstructured":"Reconfigurable System-On-Chip Design (December 2002), http:\/\/www.arl.wustl.edu\/~lockwood\/class\/cs536\/"},{"key":"83_CR11","unstructured":"Lim, D., Neely, C.E., Zuver, C.K., Lockwood, J.W.: Internet-based tool for system-on-chip integration. In: International Conference on Microelectronic Systems Education (MSE), Anaheim, CA (June 2003)"},{"key":"83_CR12","unstructured":"Neely, C.E., Zuver, C.K., Lockwood, J.W.: Internet-based tool for system-onchip project testing and grading. In: International Conference on Microelectronic Systems Education (MSE), Anaheim, CA (June 2003)"},{"key":"83_CR13","doi-asserted-by":"crossref","unstructured":"Horta, E.L., Lockwood, J.W., Taylor, D.E., Parlour, D.: Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. In: Design Automation Conference (DAC), New Orleans, LA (June 2002)","DOI":"10.1145\/513918.514007"},{"key":"83_CR14","unstructured":"Sproull, T., Lockwood, J.W., Taylor, D.E.: Control and configuration software for a reconfigurable networking hardware platform. In: IEEE Symposium on Field- Programmable Custom Computing Machines (FCCM), Napa, CA (April 2002)"},{"key":"83_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"352","DOI":"10.1007\/3-540-44614-1_38","volume-title":"Field-Programmable Logic and Applications. The Roadmap to Reconfigurable Computing","author":"S. McMillan","year":"2000","unstructured":"McMillan, S., Guccione, S.: Partial run-time reconfiguration using JRTR. In: Gr\u00fcnbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol.\u00a01896, pp. 352\u2013360. Springer, Heidelberg (2000)"},{"key":"83_CR16","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1007\/3-540-44614-1_6","volume-title":"Field-Programmable Logic and Applications. The Roadmap to Reconfigurable Computing","author":"H. Fallside","year":"2000","unstructured":"Fallside, H., Smith, M.J.S.: Internet connected FPL. In: Gr\u00fcnbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol.\u00a01896, pp. 48\u201357. Springer, Heidelberg (2000)"},{"key":"83_CR17","doi-asserted-by":"crossref","unstructured":"Lockwood, J.W., Turner, J.S., Taylor, D.E.: Field programmable port extender (FPX) for distributed routing and queuing. In: ACM International Symposium on Field Programmable Gate Arrays (FPGA 2000), Monterey, CA, USA, February 2000, pp. 137\u2013144 (2000)","DOI":"10.1145\/329166.329196"}],"container-title":["Lecture Notes in Computer Science","Field Programmable Logic and Application"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-45234-8_83","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T14:55:28Z","timestamp":1740840928000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-45234-8_83"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"ISBN":["9783540408222","9783540452348"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-45234-8_83","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2003]]},"assertion":[{"value":"30 September 2003","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}}]}}