{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T20:17:02Z","timestamp":1725567422413},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540664574"},{"type":"electronic","value":"9783540483021"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1999]]},"DOI":"10.1007\/978-3-540-48302-1_18","type":"book-chapter","created":{"date-parts":[[2010,10,14]],"date-time":"2010-10-14T06:59:24Z","timestamp":1287039564000},"page":"175-184","source":"Crossref","is-referenced-by-count":10,"title":["Hardware-Software Codesign for Dynamically Reconfigurable Architectures"],"prefix":"10.1007","author":[{"given":"Karam S.","family":"Chatha","sequence":"first","affiliation":[]},{"given":"Ranga","family":"Vemuri","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"18_CR1","doi-asserted-by":"crossref","unstructured":"Trimberger, S., Carberry, D., Johnson, A., Wong, J.: A Time-Multiplexed FPGA. In: Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA (1997)","DOI":"10.1109\/FPGA.1997.624601"},{"key":"18_CR2","doi-asserted-by":"crossref","unstructured":"Chatha, K.S., Vemuri, R.: An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW systems. In: Proceedings of 10th IEEE International Workshop on Rapid System Prototyping, Clearwater, Florida, USA (June 1999)","DOI":"10.1109\/IWRSP.1999.779043"},{"issue":"3","key":"18_CR3","doi-asserted-by":"publisher","first-page":"29","DOI":"10.1109\/54.232470","volume":"10","author":"R. Gupta","year":"1993","unstructured":"Gupta, R., Micheli, G.D.: Hardware-software cosynthesis for digital systems. IEEE Design and Test of Computers\u00a010(3), 29\u201341 (1993)","journal-title":"IEEE Design and Test of Computers"},{"key":"18_CR4","doi-asserted-by":"crossref","unstructured":"Ernst, R., Henkel, J., Benner, T.: Hardware-software cosynthesis for microcontrollers. IEEE Design and Test of Computers, 64\u201375 (1994)","DOI":"10.1109\/54.245964"},{"key":"18_CR5","unstructured":"Chatha, K.S., Vemuri, R.: Partitioning and Pipelined Scheduling of mixed HWSW systems. In: Proceedings of 11th International Symposium on System Synthesis, Hsinchu, Taiwan (December 1998)"},{"issue":"2","key":"18_CR6","doi-asserted-by":"publisher","first-page":"125","DOI":"10.1023\/A:1008872518365","volume":"2","author":"A. Kalavade","year":"1997","unstructured":"Kalavade, A., Lee, E.A.: The Extended Partitioning Problem: Hardware\/Software Mapping, Scheduling and Implementation-Bin Selection. Journal of Design Automation for Embedded Systems\u00a02(2), 125\u2013163 (1997)","journal-title":"Journal of Design Automation for Embedded Systems"},{"key":"18_CR7","doi-asserted-by":"crossref","unstructured":"Bakshi, S., Gajski, D.D.: A Scheduling and Pipelining Algorithm for Hardware\/Software Systems. In: Proceedings of 10th International Symposium on System Synthesis, Antwerp, Belgium (September 1997)","DOI":"10.1109\/ISSS.1997.621683"},{"key":"18_CR8","volume-title":"Proceedings of 5th International Workshop on Field-Programmable Logic and Applications","author":"M. Gokhale","year":"1995","unstructured":"Gokhale, M., Marks, A.: Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Arrays. In: Proceedings of 5th International Workshop on Field-Programmable Logic and Applications. Springer, Heidelberg (1995)"},{"key":"18_CR9","unstructured":"Vasilko, M., Ait-Boudaoud, D.: Scheduling for Dynamically Reconfigurable FPGAs. In: Proceedings of International Workshop on Logic and Architecture Synthesis, IFIP TC10 WG10.5, Grenoble, France (December 1995)"},{"key":"18_CR10","unstructured":"Gajjala Purna, K.M., Bhatia, D.: Temporal partitioning and scheduling for reconfigurable computing. In: Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines (1998)"},{"key":"18_CR11","doi-asserted-by":"crossref","unstructured":"Kaul, M., Vemuri, R.: Temporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. In: Proceedings of Design, Automation and Test in Europe Conference, Munich, Germany (March 1999)","DOI":"10.1145\/307418.307490"},{"key":"18_CR12","doi-asserted-by":"crossref","unstructured":"Maestre, R., Kurdahi, F.J., Bagerzadeh, N., Singh, H., Hermida, R., Fernandez, M.: Kernel Scheduling in Reconfigurable Computing. In: Proceedings of Design, Automation and Test in Europe Conference, Munich, Germany (March 1999)","DOI":"10.1145\/307418.307460"}],"container-title":["Lecture Notes in Computer Science","Field Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-48302-1_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,5]],"date-time":"2019-06-05T12:56:23Z","timestamp":1559739383000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-48302-1_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999]]},"ISBN":["9783540664574","9783540483021"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-48302-1_18","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[1999]]}}}