{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:03:01Z","timestamp":1774630981134,"version":"3.50.1"},"publisher-location":"Berlin, Heidelberg","reference-count":8,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540664574","type":"print"},{"value":"9783540483021","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1999]]},"DOI":"10.1007\/978-3-540-48302-1_28","type":"book-chapter","created":{"date-parts":[[2010,10,14]],"date-time":"2010-10-14T06:59:24Z","timestamp":1287039564000},"page":"274-281","source":"Crossref","is-referenced-by-count":35,"title":["A New Switch Block for Segmented FPGAs"],"prefix":"10.1007","author":[{"given":"M. Imran","family":"Masud","sequence":"first","affiliation":[]},{"given":"Steven J. E.","family":"Wilton","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"28_CR1","doi-asserted-by":"crossref","unstructured":"Rose, J., Hill, D.: Architectural and physical design challenges for one-million gate FPGAs and beyond. In: Proceedings of the ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, February 1997, pp. 129\u2013132 (1997)","DOI":"10.1145\/258305.258324"},{"key":"28_CR2","unstructured":"Xilinx, Inc., The Programmable Logic Data Book (1994)"},{"key":"28_CR3","unstructured":"Lemieux, G.G., Brown, S.D.: A detailed router for allocating wire segments in field-programmable gate arrays. In: Proceedings of the ACM Physical Design Workshop (April 1993)"},{"key":"28_CR4","doi-asserted-by":"publisher","first-page":"80","DOI":"10.1145\/225871.225886","volume":"1","author":"Y.-W. Chang","year":"1996","unstructured":"Chang, Y.-W., Wong, D., Wong, C.: Universal switch modules for FPGA design. ACM Transactions on Design Automation of Electronic Systems\u00a01, 80\u2013101 (1996)","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"28_CR5","unstructured":"Wilton, S.J.E.: Architectures and Algorithms for Field-Programmable Gate Arrays with Embedded Memory. PhD thesis, University of Toronto (1997)"},{"key":"28_CR6","unstructured":"Betz, V.: Architecture and CAD for Speed and Area Optimizations of FPGAs. PhD thesis, University of Toronto (1998)"},{"key":"28_CR7","doi-asserted-by":"crossref","unstructured":"Betz, V., Rose, J.: FPGA routing architecture: Segmentation and buffering to optimize speed and density. In: Proceedings of the ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (February 1999)","DOI":"10.1145\/296399.296428"},{"key":"28_CR8","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/43.273754","volume":"13","author":"J. Cong","year":"1994","unstructured":"Cong, J., Ding, Y.: FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a013, 1\u201312 (1994)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"}],"container-title":["Lecture Notes in Computer Science","Field Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-48302-1_28","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,21]],"date-time":"2019-03-21T17:09:56Z","timestamp":1553188196000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-48302-1_28"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999]]},"ISBN":["9783540664574","9783540483021"],"references-count":8,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-48302-1_28","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[1999]]}}}