{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T05:29:34Z","timestamp":1725514174882},"publisher-location":"Berlin, Heidelberg","reference-count":9,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540685548"},{"type":"electronic","value":"9783540685555"}],"license":[{"start":{"date-parts":[[2008,1,1]],"date-time":"2008-01-01T00:00:00Z","timestamp":1199145600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008]]},"DOI":"10.1007\/978-3-540-68555-5_27","type":"book-chapter","created":{"date-parts":[[2008,5,23]],"date-time":"2008-05-23T13:28:10Z","timestamp":1211549290000},"page":"324-346","source":"Crossref","is-referenced-by-count":0,"title":["Formal Specification of the OpenMP Memory Model"],"prefix":"10.1007","author":[{"given":"Greg","family":"Bronevetsky","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bronis R.","family":"de Supinski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"27_CR1","unstructured":"OpenMP Architecture\u00a0Review Board. OpenMP application program interface, version 2.5"},{"key":"27_CR2","unstructured":"Bronevetsky, G., de Supinski, B.: Fully formal specification of the OpenMP memory model. Cornell Computer Science (in preparation) (2005)"},{"key":"27_CR3","unstructured":"Collier, W.W.: Reasoning About Parallel Architectures (1992)"},{"key":"27_CR4","doi-asserted-by":"crossref","unstructured":"Scheurich, C., Dubois, M., Briggs, F.: Memory access buffering in multiprocessors. In: Proceedings of the 13th Annual International Symposium on Computer Architecture (ISCA), pp. 434\u2013442 (1986)","DOI":"10.1145\/17356.17406"},{"key":"27_CR5","unstructured":"Goodman, J.R.: Cache consistency and sequential consistency. Technical Report\u00a061, SCI Committee (1989)"},{"key":"27_CR6","unstructured":"Hoeflinger, J., de Supinski, B.: The openmp memory model. In: International Workshop on OpenMP (IWOMP) (2005)"},{"key":"27_CR7","doi-asserted-by":"crossref","unstructured":"Pugh., W., Manson., J., Adve, S.V.: The java memory model. In: Symposium on Principles of Programming Languages (POPL ) (2005)","DOI":"10.1145\/1040305.1040336"},{"issue":"2","key":"27_CR8","doi-asserted-by":"publisher","first-page":"125","DOI":"10.1023\/A:1022969405325","volume":"22","author":"J. Matthews","year":"2003","unstructured":"Matthews, J., Tasiran, S., Tuttle, M., Joshi, R., Lamport, L., Yu, Y.: Checking cache-coherence protocols with tla+. Formal Methods in System Design\u00a022(2), 125\u2013131 (2003)","journal-title":"Formal Methods in System Design"},{"key":"27_CR9","unstructured":"Robinson, A., Voronkov, A. (eds.): Handbook of Automated Reasoning (2000)"}],"container-title":["Lecture Notes in Computer Science","OpenMP Shared Memory Parallel Programming"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-68555-5_27","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,19]],"date-time":"2019-05-19T15:32:18Z","timestamp":1558279938000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-68555-5_27"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008]]},"ISBN":["9783540685548","9783540685555"],"references-count":9,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-68555-5_27","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2008]]}}}