{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,31]],"date-time":"2025-01-31T05:15:44Z","timestamp":1738300544040,"version":"3.35.0"},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540695004"},{"type":"electronic","value":"9783540695011"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-69501-1_19","type":"book-chapter","created":{"date-parts":[[2008,6,2]],"date-time":"2008-06-02T07:20:45Z","timestamp":1212391245000},"page":"173-184","source":"Crossref","is-referenced-by-count":4,"title":["A Non-blocking Multithreaded Architecture with Support for Speculative Threads"],"prefix":"10.1007","author":[{"given":"Krishna","family":"Kavi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wentong","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali","family":"Hurson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"doi-asserted-by":"crossref","unstructured":"Agarwal, V., Hrishikesh, M.S., Keckler, S.W., Burger, D.: Clock Rate Versus IPC: The End of the Road for Conventional Microarchitectures. In: 27th International Symposium on Computer Architecture (ISCA), June 2000, pp. 248\u2013259 (2000)","key":"19_CR1","DOI":"10.1145\/339647.339691"},{"doi-asserted-by":"crossref","unstructured":"Tullsen, D.M., Eggers, S.J., Levy, H.M., Lo, J.L.: Simultaneous multithreading: Maximizing on-chip parallelism. In: International. Symposium on Computer Architecture (ISCA), June 1995, pp. 392\u2013403 (1995)","key":"19_CR2","DOI":"10.1145\/225830.224449"},{"doi-asserted-by":"crossref","unstructured":"Sankaralingam, K., Nagarajan, R., Liu, H., Huh, J., Kim, C.K., Burger, D., Keckler, S.W., Moore, C.R.: Exploiting ILP, TLP, and DLP Using Polymorphism in the TRIPS Architecture. In: 30th International Symposium on Computer Architecture (ISCA), June 2003, pp. 422\u2013433 (2003)","key":"19_CR3","DOI":"10.1145\/859618.859667"},{"doi-asserted-by":"crossref","unstructured":"Burger, D., et al.: Scaling to the end of silicon with EDGE architectures. IEEE Computer, 44\u201355 (July 2004)","key":"19_CR4","DOI":"10.1109\/MC.2004.65"},{"doi-asserted-by":"crossref","unstructured":"Swanson, S., Michelson, K., Schwerin, A., Oskin, M.: WaveScalar. In: Proceedings of the 36th International Symposium on Microarchitecture(MICRO), December 2003, pp. 291\u2013302 (2003)","key":"19_CR5","DOI":"10.1109\/MICRO.2003.1253203"},{"doi-asserted-by":"crossref","unstructured":"Onder, S., Gupta, R.: Superscalar execution with direct data forwarding. In: Proc of the International Conference on Parallel Architectures and Compiler Technologies, Paris, October 1998, pp. 130\u2013135 (1998)","key":"19_CR6","DOI":"10.1109\/PACT.1998.727183"},{"doi-asserted-by":"crossref","unstructured":"Marcuello, P., Gonzalez, A., Tubella, J.: Speculative Multithreaded Processors. In: Proceeding of the International Conference on Supercomputing, July 1998, pp. 77\u201384 (1998)","key":"19_CR7","DOI":"10.1145\/277830.277850"},{"doi-asserted-by":"crossref","unstructured":"Zhang, Y., Rauchwerger, L., Torrelas, J.: Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. In: 5th International Symposium on High-Performance Computer Architecture (HPCA), January 1999, pp. 135\u2013141 (1999)","key":"19_CR8","DOI":"10.1109\/HPCA.1999.744351"},{"doi-asserted-by":"crossref","unstructured":"Steffan, J.G., Colohan, C.B., Zhai, A., Mowry, T.C.: A Scalable Approach to Thread-Level Speculation. In: 27th International Symposium on Computer Architecture (ISCA), June 2000, pp. 1\u201312 (2000)","key":"19_CR9","DOI":"10.1145\/339647.339650"},{"issue":"11","key":"19_CR10","doi-asserted-by":"publisher","first-page":"598","DOI":"10.1145\/69558.69562","volume":"4","author":"Arvind","year":"1989","unstructured":"Arvind, Nikhil, R.S., Pingali, K.K.: Istructures: Data-structures for parallel computing. ACM Transactions on Programming Languages and Systems\u00a04(11), 598\u2013632 (1989)","journal-title":"ACM Transactions on Programming Languages and Systems"},{"unstructured":"Burger, D., Austin, T.M.: The SimpleScalar Tool Set Version 2.0, Tech Rept. #1342, Department of Computer Science, University of Wisconsin, Madison, WI","key":"19_CR11"},{"doi-asserted-by":"crossref","unstructured":"Terada, H., Miyata, S., Iwata, M.: DDMP\u2019s: Self-timed Super-pipelined Data-driven Multimedia Processor. Proceedings of the IEEE, 282\u2013296 (February 1999)","key":"19_CR12","DOI":"10.1109\/5.740021"},{"unstructured":"Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 3rd edn. (2003)","key":"19_CR13"},{"key":"19_CR14","doi-asserted-by":"publisher","first-page":"53","DOI":"10.1016\/S0065-2458(08)60706-8","volume":"45","author":"A.R. Hurson","year":"1997","unstructured":"Hurson, A.R., Lim, J.T., Kavi, K.M., Lee, B.: Parallelization of DOALL and DOACROSS Loops \u2013 A Survey. Advances in Computers\u00a045, 53\u2013103 (1997)","journal-title":"Advances in Computers"},{"doi-asserted-by":"crossref","unstructured":"Magklis, G., et al.: Dynamic Frequency and Voltage Scaling for a Multiple Clock Domain Microprocessor. IEEE Micro, 62\u201369 (November\/December 2003)","key":"19_CR15","DOI":"10.1109\/MM.2003.1261388"},{"doi-asserted-by":"crossref","unstructured":"Semeraro, G., et al.: Dynamic frequency and voltage control for multiple clock domain microarchitecture. In: Proc. of International symposium on microarchitecture (MICRO-35), pp. 356\u2013370 (2002)","key":"19_CR16","DOI":"10.1109\/MICRO.2002.1176263"},{"doi-asserted-by":"crossref","unstructured":"Jain, R., Hughes, C.J., Adve, S.V.: Soft Real-Time Scheduling on Simultaneous Multithreaded Processors. In: Proceedings of the 23rd IEEE International Real-Time Systems Symposium (December 2002)","key":"19_CR17","DOI":"10.1109\/REAL.2002.1181569"}],"container-title":["Lecture Notes in Computer Science","Algorithms and Architectures for Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-69501-1_19.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,30]],"date-time":"2025-01-30T14:38:32Z","timestamp":1738247912000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-69501-1_19"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540695004","9783540695011"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-69501-1_19","relation":{},"subject":[]}}