{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T16:22:25Z","timestamp":1759335745673},"publisher-location":"Berlin, Heidelberg","reference-count":25,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540705499"},{"type":"electronic","value":"9783540705505"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-70550-5_13","type":"book-chapter","created":{"date-parts":[[2008,7,17]],"date-time":"2008-07-17T14:19:16Z","timestamp":1216304356000},"page":"116-125","source":"Crossref","is-referenced-by-count":4,"title":["Area Reliability Trade-Off in Improved Reed Muller Coding"],"prefix":"10.1007","author":[{"given":"Costas","family":"Argyrides","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephania","family":"Loizidou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dhiraj K.","family":"Pradhan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"13_CR1","doi-asserted-by":"crossref","unstructured":"Bertozzi, D., et al.: Error control schemes for on-chip communication links: the energy-reliability tradeoff. IEEE Trans. on DAC\u00a024(6) (June 2005)","DOI":"10.1109\/TCAD.2005.847907"},{"issue":"5","key":"13_CR2","doi-asserted-by":"publisher","first-page":"511","DOI":"10.1023\/A:1025117828910","volume":"19","author":"D. Rossi","year":"2003","unstructured":"Rossi, D., Metra, C.: Error correcting strategy for high speed and density reliable flash memories. IEEE J. Electronic Testing, Theory and applications\u00a019(5), 511\u2013521 (2003)","journal-title":"IEEE J. Electronic Testing, Theory and applications"},{"key":"13_CR3","doi-asserted-by":"crossref","unstructured":"Nicolaidis, M.: Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies. In: 17th IEEE VLSI Test Symposium, p. 86 (1999)","DOI":"10.1109\/VTEST.1999.766651"},{"issue":"2","key":"13_CR4","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1109\/MC.2005.70","volume":"38","author":"S. Mitra","year":"2005","unstructured":"Mitra, S., et al.: Robust System Design with Built-In Soft-Error Resilience. IEEE computer society\u00a038(2), 43\u201352 (2005)","journal-title":"IEEE computer society"},{"key":"13_CR5","doi-asserted-by":"publisher","first-page":"778","DOI":"10.1109\/4.102676","volume":"25","author":"K. Itoh","year":"1990","unstructured":"Itoh, K.: Trends in megabit DRAM circuit design. IEEE J. Solid State Circuits\u00a025, 778\u2013789 (1990)","journal-title":"IEEE J. Solid State Circuits"},{"key":"13_CR6","doi-asserted-by":"publisher","first-page":"524","DOI":"10.1109\/5.371965","volume":"83","author":"K. Itoh","year":"1995","unstructured":"Itoh, K., et al.: Trends in low-power RAM circuit technologies. Proc. IEEE\u00a083, 524\u2013543 (1995)","journal-title":"Proc. IEEE"},{"key":"13_CR7","doi-asserted-by":"publisher","first-page":"381","DOI":"10.1109\/JSSC.1986.1052538","volume":"SSC-21","author":"K. Kimura","year":"1986","unstructured":"Kimura, K., et al.: Power reduction in megabit DRAM\u2019s. IEEE Journal of Solid State Circuits\u00a0SSC-21, 381\u2013389 (1986)","journal-title":"IEEE Journal of Solid State Circuits"},{"key":"13_CR8","unstructured":"International Technology Road map for Semiconductors (2002), http:\/\/public.itrs.net\/"},{"key":"13_CR9","doi-asserted-by":"publisher","first-page":"466","DOI":"10.1109\/TNS.2003.813131","volume":"50","author":"J.L. Barth","year":"2003","unstructured":"Barth, J.L., Dyer, C.S., Stassinopoulos, E.G.: Space, atmospheric, and terrestrial radiation environments. IEEE Trans. Nuclear Science\u00a050, 466\u2013482 (2003)","journal-title":"IEEE Trans. Nuclear Science"},{"issue":"6","key":"13_CR10","doi-asserted-by":"publisher","first-page":"2586","DOI":"10.1109\/23.903813","volume":"47","author":"P. Hazucha","year":"2000","unstructured":"Hazucha, P., Svensson, C.: Impact of CMOS technology scaling on the atmospheric neutron soft error rate. IEEE Trans. Nucl. Sci.\u00a047(6), 2586\u20132594 (2000)","journal-title":"IEEE Trans. Nucl. Sci."},{"issue":"1","key":"13_CR11","doi-asserted-by":"publisher","first-page":"494","DOI":"10.1109\/TNS.2005.845883","volume":"52","author":"P.A. Ferreyra","year":"2005","unstructured":"Ferreyra, P.A., Marques, C.A., Ferreyra, R.T., Gaspar, J.P.: Failure map functions and accelerated mean time to failure tests: New approaches for improving the reliability estimation in systems exposed to single event upsets. IEEE Trans. Nucl. Sci.\u00a052(1), 494\u2013500 (2005)","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"13_CR12","doi-asserted-by":"crossref","unstructured":"Hentschke, R., Marques, R., Lima, F., Carro, L., Susin, A., Reis, R.: Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy. In: Symposium on Integrated Circuits and Systems Design, pp. 95\u2013100 (2002)","DOI":"10.1109\/SBCCI.2002.1137643"},{"key":"13_CR13","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1109\/40.259894","volume":"14","author":"J. Karlsson","year":"1994","unstructured":"Karlsson, J., Liden, P., Dahlgren, P., Johansson, R., Gunneflo, U.: Using Heavy-Ion Radiation to Validate Fault-Handling Mechanisms. IEEE Micro.\u00a014, 8\u201323 (1994)","journal-title":"IEEE Micro."},{"key":"13_CR14","doi-asserted-by":"crossref","unstructured":"Reed, R.: Heavy Ion and Proton Induced Single Event Multiple Upsets. In: IEEE Nuclear and Space Radiation Effects Conference, pp. 2224\u20132229 (1997)","DOI":"10.1109\/23.659039"},{"key":"13_CR15","doi-asserted-by":"crossref","unstructured":"Seifert, N., Moyer, D., Leland, N., Hokinson, R.: Historical trend in alpha-particle induced soft error rates of the Alpha microprocessor. In: Proc. 39th Annu. IEEE Int. Reliab. Phys. Symp., pp. 259\u2013265 (2001)","DOI":"10.1109\/RELPHY.2001.922911"},{"key":"13_CR16","doi-asserted-by":"crossref","unstructured":"Hsiao, M.Y.: A class of Optimal Minimum Odd-Weight column SEC-DED codes. IBM J. of Research and Dev.\u00a0(14), 395\u2013401 (July 1970)","DOI":"10.1147\/rd.144.0395"},{"key":"13_CR17","doi-asserted-by":"crossref","unstructured":"Prahdan, D.K., Reddy, S.M.: Error-Control Techniques for Logic Processors. IEEE Trans. on Comp.\u00a0C-21(12) (December 1972)","DOI":"10.1109\/T-C.1972.223504"},{"issue":"4","key":"13_CR18","doi-asserted-by":"publisher","first-page":"38","DOI":"10.1109\/TIT.1954.1057465","volume":"4","author":"Reed","year":"1954","unstructured":"Reed.: A class of multiple-error-correcting codes and the decoding scheme. IEEE Trans. on Information Theory\u00a04(4), 38\u201349 (1954)","journal-title":"IEEE Trans. on Information Theory"},{"volume-title":"Designs and their Codes","year":"1992","key":"13_CR19","unstructured":"Assmus Jr., E.F., Key, J.D. (eds.): Designs and their Codes. Press Syndicate of the University of Cambridge, Cambridge (1992)"},{"key":"13_CR20","unstructured":"Roman, S.: Coding and information Theory. Graduate Texts in Mathematics (1992)"},{"key":"13_CR21","volume-title":"Error-Control Coding for Computer Systems","author":"T.R.N. Rao","year":"1989","unstructured":"Rao, T.R.N., Fujiwara, E.: Error-Control Coding for Computer Systems. Prentice Hall, New Jersey (1989)"},{"key":"13_CR22","doi-asserted-by":"crossref","unstructured":"Argyrides, C., Pradhan, D.K.: Improved Decoding Algorithm for High Reliable Reed Muller Coding. In: 20th IEEE International System On Chip Conference (SOCC 2007) (September 2007)","DOI":"10.1109\/SOCC.2007.4545435"},{"issue":"1","key":"13_CR23","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1109\/PGEC.1964.263829","volume":"14","author":"C.S. Wallace","year":"1964","unstructured":"Wallace, C.S.: A Suggestion for a Fast Multiplier. IEEE Trans. On Electronic Computer\u00a0EC-14(1), 14\u201317 (1964)","journal-title":"IEEE Trans. On Electronic Computer"},{"key":"13_CR24","doi-asserted-by":"crossref","unstructured":"Kinichiroh, T., et al.: New Decoding Algorithm for Reed-Muller Codes. IEEE Trans. on Infornation. Theory\u00a0IT-28(5) (September 1982)","DOI":"10.1109\/TIT.1982.1056554"},{"key":"13_CR25","doi-asserted-by":"crossref","unstructured":"Argyrides, C., Zarandi, H., Pradhan, D.: Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. In: 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2007) (September 2007)","DOI":"10.1109\/DFT.2007.29"}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-70550-5_13.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,5,3]],"date-time":"2021-05-03T04:22:04Z","timestamp":1620015724000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-70550-5_13"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540705499","9783540705505"],"references-count":25,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-70550-5_13","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[]}}