{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T04:53:29Z","timestamp":1725512009507},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540709510"},{"type":"electronic","value":"9783540709527"}],"license":[{"start":{"date-parts":[[2007,1,1]],"date-time":"2007-01-01T00:00:00Z","timestamp":1167609600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1007\/978-3-540-70952-7_10","type":"book-chapter","created":{"date-parts":[[2007,6,26]],"date-time":"2007-06-26T08:40:01Z","timestamp":1182847201000},"page":"148-164","source":"Crossref","is-referenced-by-count":0,"title":["Verifying VHDL Designs with Multiple Clocks in SMV"],"prefix":"10.1007","author":[{"given":"A.","family":"Smr\u010dka","sequence":"first","affiliation":[]},{"given":"V.","family":"\u0158eh\u00e1k","sequence":"additional","affiliation":[]},{"given":"T.","family":"Vojnar","sequence":"additional","affiliation":[]},{"given":"D.","family":"\u0160afr\u00e1nek","sequence":"additional","affiliation":[]},{"given":"P.","family":"Matou\u0161ek","sequence":"additional","affiliation":[]},{"given":"Z.","family":"\u0158eh\u00e1k","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"10_CR1","volume-title":"System-on-a-chip Verification. Methodology & Techniques","author":"P. Rashinka","year":"2001","unstructured":"Rashinka, P., et al.: System-on-a-chip Verification. Methodology & Techniques. Kluwer Academic Publishers, Dordrecht (2001)"},{"key":"10_CR2","series-title":"Lecture Notes in Computer Science","volume-title":"Computer Aided Verification","author":"R.K. Brayton","year":"1996","unstructured":"Brayton, R.K., et al.: VIS: A System for Verification and Synthesis. In: Alur, R., Henzinger, T.A. (eds.) CAV 1996. LNCS, vol.\u00a01102, Springer, Heidelberg (1996)"},{"key":"10_CR3","unstructured":"Mentor Graphics. Leonardo Synthesis (2005)"},{"key":"10_CR4","unstructured":"Mentor Graphics. 0-In Formal Verification Data Sheet (2006)"},{"key":"10_CR5","unstructured":"Mentor Graphics. Formal Pro Data Sheet (2006)"},{"key":"10_CR6","unstructured":"Hole\u010dek, J., Kratochv\u00edla, T., \u0158eh\u00e1k, V., \u0160afr\u00e1nek, D., Sime\u010dek, P.: Verification Process of Hardware Design in Liberouter Project. Technical Report 5\/2004, CESNET (2004)"},{"key":"10_CR7","volume-title":"Proc. of FPL\u201905","author":"J. Ko\u0159enek","year":"2005","unstructured":"Ko\u0159enek, J., Pe\u010denka, T., \u017d\u00e1dn\u00edk, M.: NetFlow Probe Intended for High-Speed Networks. In: Proc. of FPL\u201905, IEEE Computer Society Press, Los Alamitos (2005)"},{"key":"10_CR8","unstructured":"Ko\u0159enek, J., Zem\u010d\u00edk, P., Mart\u00ednek, T.: FPGA-Based Platform for Network Applications. In: Proc. of DDECS\u201905, University of West Hungary (2005)"},{"key":"10_CR9","unstructured":"Kratochv\u00edla, T., \u0158eh\u00e1k, V., \u0160afr\u00e1nek, D.: Formal Verification of a FIFO Component in Design of Network Monitoring Hardware. In: Proc. of CESNET 2006 Conference (2006)"},{"key":"10_CR10","unstructured":"Liberouter Project Homepage. \n                    \n                      http:\/\/www.liberouter.org"},{"key":"10_CR11","unstructured":"Ly, T., Hand, N., Kwok, C.K.-k.: Formally Verifying Clock Domain Crossing Jitter Using Assertion-Based Verification. In: Proc of DVCon\u201904 (2004)"},{"key":"10_CR12","unstructured":"Matou\u0161ek, P., Smr\u010dka, A., Vojnar, T.: Modeling, Analysis, and Verification of SCAMPI2. Technical Report 8\/2005, CESNET (2005)"},{"key":"10_CR13","unstructured":"McMillan, K.L.: Cadence SMV Manual (2006)"},{"key":"10_CR14","volume-title":"Digital Design: Principles and Practices","author":"J.F. Wakerly","year":"2001","unstructured":"Wakerly, J.F.: Digital Design: Principles and Practices, 3rd edn. Prentice-Hall, Englewood Cliffs (2001)","edition":"3"}],"container-title":["Lecture Notes in Computer Science","Formal Methods: Applications and Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-70952-7_10","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,19]],"date-time":"2019-05-19T09:59:58Z","timestamp":1558259998000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-70952-7_10"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"ISBN":["9783540709510","9783540709527"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-70952-7_10","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2007]]}}}