{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T05:19:10Z","timestamp":1737091150249,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540712671"},{"type":"electronic","value":"9783540712701"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-71270-1_7","type":"book-chapter","created":{"date-parts":[[2007,5,20]],"date-time":"2007-05-20T23:50:51Z","timestamp":1179705051000},"page":"83-97","source":"Crossref","is-referenced-by-count":1,"title":["A Multiprocessor Cache for Massively Parallel SoC Architectures"],"prefix":"10.1007","author":[{"given":"J\u00f6rg-Christian","family":"Niemann","sequence":"first","affiliation":[]},{"given":"Christian","family":"Li\u00df\u0308","sequence":"additional","affiliation":[]},{"given":"Mario","family":"Porrmann","sequence":"additional","affiliation":[]},{"given":"Ulrich","family":"R\u00fcckert","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"7_CR1","first-page":"583","volume-title":"Proceedings of the Workshop on High-Speed Local Networks held in conjunction with the 28th Annual IEEE Conference on Local Computer Networks","author":"O. Bonorden","year":"2003","unstructured":"Bonorden, O., Br\u00fcls, N., Le, D.K., Kastens, U., Meyer auf der Heide, F., Niemann, J.-C., Porrmann, M., R\u00fcckert, U., Slowik, A., Thies, M.: A holistic methodology for network processor design. In: Proceedings of the Workshop on High-Speed Local Networks held in conjunction with the 28th Annual IEEE Conference on Local Computer Networks, October 20-24, pp. 583\u2013592. IEEE Computer Society Press, Los Alamitos (2003)"},{"key":"7_CR2","volume-title":"IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL","author":"J.-C. Niemann","year":"2005","unstructured":"Niemann, J.-C., Porrmann, M., R\u00fcckert, U., Scalable, A.: Parallel SoC Architecture for Network Processors. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, IEEE Computer Society Press, Los Alamitos (2005)"},{"key":"7_CR3","unstructured":"Li\u00df, C.: Implementation of an AMBA AHB Interconnection Matrix. Technical Report. University of Paderborn, Paderborn, Germany (May 2004)"},{"key":"7_CR4","volume-title":"Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany","author":"H. Kalte","year":"2002","unstructured":"Kalte, H., Porrmann, M., R\u00fcckert, U.: A Prototyping Platform for Dynamically Reconfigurable System on Chip Designs. In: Proceedings of the IEEE Workshop Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, IEEE Press, Los Alamitos (2002)"},{"key":"7_CR5","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"268","DOI":"10.1007\/11682127_19","volume-title":"Architecture of Computing Systems - ARCS 2006","author":"J.-C. Niemann","year":"2006","unstructured":"Niemann, J.-C., Puttmann, C., Porrmann, M., R\u00fcckert, U.: GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. In: Grass, W., Sick, B., Waldschmidt, K. (eds.) ARCS 2006. LNCS, vol.\u00a03894, pp. 268\u2013282. Springer, Heidelberg (2006)"},{"key":"7_CR6","volume-title":"Proc. of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany","author":"D. Langen","year":"2002","unstructured":"Langen, D., Niemann, J.-C., Porrmann, M., Kalte, H., R\u00fcckert, U.: Implementation of a RISC Processor Core for SoC Designs FPGA Prototype vs. ASIC Implementation. In: Proc. of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany, IEEE Press, Los Alamitos (2002)"},{"key":"7_CR7","doi-asserted-by":"crossref","unstructured":"Gr\u00fcnewald, M., Kastens, U., Le, D.K., Niemann, J.-C., Porrmann, M., R\u00fcckert, U., Thies, M., Slowik, A.: Network Application Driven Instruction Set Extensions for Embedded Processing Clusters. In: PARELEC 2004, International Conference on Parallel Computing in Electrical Engineering, Dresden, Germany, pp. 209\u2013214 (2004)","DOI":"10.1109\/PCEE.2004.1335612"},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"Eickhoff, R., Niemann, J.-C., Porrmann, M., R\u00fcckert, U.: Adaptable Switch boxes as on-chip routing nodes for networks-on-chip. In: Rettberg, A., Zanella, M.C., Rammig, F.J. (eds.) From Specification to Embedded Systems Application, International Embedded Systems Symposium (IESS), Manaus, Brazil, 15-17 August, pp. 201\u201321 (2005)","DOI":"10.1007\/11523277_20"},{"key":"7_CR9","doi-asserted-by":"crossref","unstructured":"Dally, W.J., Towles, B.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: Proceedings of the Design Automation Conference, Las Vegas, Nevada, USA, June 18-22, pp. 684\u2013689 (2001)","DOI":"10.1109\/DAC.2001.935594"},{"key":"7_CR10","unstructured":"Niemann, J.-C., Porrmann, M., Sauer, C., R\u00fcckert, U.: An Evaluation of the Scalable GigaNetIC Architecture for Access Networks. In: Advanced Networking and Communications Hardware Workshop (ANCHOR), held in conjunction with the ISCA 2005, Advanced Networking and Communications (2005)"},{"key":"7_CR11","doi-asserted-by":"crossref","unstructured":"St\u00fcmpel, E., Thies, M., Kastens, U.: VLIW Compilation Techniques for Superscalar Architectures. In: Koskimies, K. (ed.) Proc. of 7th International Conference on Compiler Construction CC\u201998 (1998)","DOI":"10.1007\/BFb0026418"},{"key":"7_CR12","volume-title":"Proceedings of ACM SIGPLAN\/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES\u201904)","author":"U. Kastens","year":"2004","unstructured":"Kastens, U., Le, D.K., Slowik, A., Thies, M.: Feedback Driven Instruction-Set Extension. In: Proceedings of ACM SIGPLAN\/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES\u201904), Washington, D.C., USA, June, ACM Press, New York (2004)"},{"issue":"3","key":"7_CR13","doi-asserted-by":"publisher","first-page":"13","DOI":"10.1145\/268806.268810","volume":"25","author":"D. Burger","year":"1997","unstructured":"Burger, D., Austin, T.M.: The SimpleScalar tool set, version 2.0. SIGARCH Computer Architecture News\u00a025(3), 13\u201325 (1997)","journal-title":"SIGARCH Computer Architecture News"},{"key":"7_CR14","unstructured":"Tarjan, D., Thoziyoor, S., Jouppi, N.P.: CACTI 4.0. Technical Report. HP Laboratories Palo Alto, Palo Alto, CA, USA (June 2006)"},{"key":"7_CR15","doi-asserted-by":"publisher","first-page":"396","DOI":"10.1145\/1064212.1064272","volume-title":"SIGMETRICS \u201905: Proceedings of the 2005 ACM SIGMETRICS international conference on Measurement and modeling of computer systems","author":"J. Mudigonda","year":"2005","unstructured":"Mudigonda, J., Vin, H., Yavatkar, R.: Managing Memory Access Latency in Packet Processing. In: SIGMETRICS \u201905: Proceedings of the 2005 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, Banff, Alberta, Canada, June, pp. 396\u2013397. ACM Press, New York (2005)"},{"key":"7_CR16","unstructured":"Tensilica. Xtensa, L.X.: Microprocessor, Overview Handbook. Internet publication, Santa Clara, CA, USA (2004), Source: http:\/\/tensilica.com\/pdf\/xtensalx_overview_handbook.pdf , Seen online: 05.10.2006"},{"key":"7_CR17","unstructured":"ARC International: ARC 700 configurable core family. Internet publication. San Jose, CA, USA (2005), Source: http:\/\/arc.com\/evaluations\/ARC_700_Family.pdf , Seen online: 05.10.2006"},{"key":"7_CR18","doi-asserted-by":"crossref","unstructured":"Sweazey, P., Smith, A.J.: A class of compatible cache consistency protocols and their support by the IEEE futurebus. In: 13th Annual International Symposium on Computer Architecture, ISCA, Japan (1986)","DOI":"10.1145\/17356.17404"}],"container-title":["Lecture Notes in Computer Science","Architecture of Computing Systems - ARCS 2007"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-71270-1_7.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,16]],"date-time":"2025-01-16T14:18:53Z","timestamp":1737037133000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-71270-1_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540712671","9783540712701"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-71270-1_7","relation":{},"subject":[]}}