{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,27]],"date-time":"2025-03-27T21:01:36Z","timestamp":1743109296096,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":33,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540715276"},{"type":"electronic","value":"9783540715283"}],"license":[{"start":{"date-parts":[[2007,1,1]],"date-time":"2007-01-01T00:00:00Z","timestamp":1167609600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1007\/978-3-540-71528-3_11","type":"book-chapter","created":{"date-parts":[[2007,7,20]],"date-time":"2007-07-20T16:02:55Z","timestamp":1184947375000},"page":"159-178","source":"Crossref","is-referenced-by-count":10,"title":["Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations"],"prefix":"10.1007","author":[{"given":"Harald","family":"Devos","sequence":"first","affiliation":[]},{"given":"Kristof","family":"Beyls","sequence":"additional","affiliation":[]},{"given":"Mark","family":"Christiaens","sequence":"additional","affiliation":[]},{"given":"Jan","family":"Van Campenhout","sequence":"additional","affiliation":[]},{"given":"Erik H.","family":"D\u2019Hollander","sequence":"additional","affiliation":[]},{"given":"Dirk","family":"Stroobandt","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"11_CR1","unstructured":"http:\/\/www.impulsec.com\/"},{"key":"11_CR2","volume-title":"Compilers: Principles, Techniques and Tools","author":"A.V. Aho","year":"1986","unstructured":"Aho, A.V., Sethi, R., Ullman, J.D.: Compilers: Principles, Techniques and Tools. Addison-Wesley, Reading (1986)"},{"key":"11_CR3","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3628-4","volume-title":"Sequential logic synthesis","author":"P. Ashar","year":"1992","unstructured":"Ashar, P., Devadas, S., Newton, A.R.: Sequential logic synthesis. Kluwer Academic Publishers, Dordrecht (1992)"},{"issue":"12","key":"11_CR4","doi-asserted-by":"publisher","first-page":"1811","DOI":"10.1109\/TCAD.2005.852431","volume":"24","author":"I. Aug\u00e9","year":"2005","unstructured":"Aug\u00e9, I., P\u00e9trot, F., Donnet, F., Gomez, P.: Platform-based design from parallel C specifications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems\u00a024(12), 1811\u20131826 (2005)","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"11_CR5","doi-asserted-by":"crossref","unstructured":"Bastoul, C.: Code generation in the polyhedral model is easier than you think. In: PACT, pp. 7\u201316 (2004)","DOI":"10.1109\/PACT.2004.1342537"},{"key":"11_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"209","DOI":"10.1007\/978-3-540-24644-2_14","volume-title":"Languages and Compilers for Parallel Computing","author":"C. Bastoul","year":"2004","unstructured":"Bastoul, C., Cohen, A., Girbal, S., Sharma, S., Temam, O.: Putting polyhedral loop transformations to work. In: Rauchwerger, L. (ed.) LCPC 2003. LNCS, vol.\u00a02958, pp. 209\u2013225. Springer, Heidelberg (2004)"},{"key":"11_CR7","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"320","DOI":"10.1007\/3-540-36579-6_23","volume-title":"Compiler Construction","author":"C. Bastoul","year":"2003","unstructured":"Bastoul, C., Feautrier, P.: Improving data locality by chunking. In: Hedin, G. (ed.) CC 2003 and ETAPS 2003. LNCS, vol.\u00a02622, pp. 320\u2013335. Springer, Heidelberg (2003)"},{"issue":"4","key":"11_CR8","doi-asserted-by":"publisher","first-page":"32","DOI":"10.1109\/54.329451","volume":"11","author":"L. Benini","year":"1994","unstructured":"Benini, L., Siegel, P., De Micheli, G.: Saving power by synthesizing gated clocks for sequential circuits. IEEE Design & Test of Computers\u00a011(4), 32\u201341 (1994)","journal-title":"IEEE Design & Test of Computers"},{"key":"11_CR9","doi-asserted-by":"crossref","unstructured":"Berg, E., Hagersten, E.: Fast data-locality profiling of native execution. In: SIGMETRICS, Banff, Alberta, Canada, pp. 169\u2013180 (2005), doi:10.1145\/1064212.1064232","DOI":"10.1145\/1064212.1064232"},{"key":"11_CR10","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"220","DOI":"10.1007\/11847366_23","volume-title":"High Performance Computing and Communications","author":"K. Beyls","year":"2006","unstructured":"Beyls, K., D\u2019Hollander, E.: Discovery of locality-improving refactorings by reuse path analysis. In: Gerndt, M., Kranzlm\u00fcller, D. (eds.) HPCC 2006. LNCS, vol.\u00a04208, pp. 220\u2013229. Springer, Heidelberg (2006)"},{"issue":"4","key":"11_CR11","doi-asserted-by":"publisher","first-page":"223","DOI":"10.1016\/j.sysarc.2004.09.004","volume":"51","author":"K. Beyls","year":"2005","unstructured":"Beyls, K., D\u2019Hollander, E.H.: Generating cache hints for improved program efficiency. Journal of Systems Architecture\u00a051(4), 223\u2013250 (2005)","journal-title":"Journal of Systems Architecture"},{"key":"11_CR12","doi-asserted-by":"crossref","unstructured":"Beyls, K., D\u2019Hollander, E.H.: Intermediately executed code is the key to find refactorings that improve temporal data locality. In: Proceedings of the 3rd conference on Computing Frontiers, pp. 373\u2013382 (2006)","DOI":"10.1145\/1128022.1128071"},{"issue":"2","key":"11_CR13","doi-asserted-by":"publisher","first-page":"117","DOI":"10.1023\/A:1013623303037","volume":"21","author":"W. Bohm","year":"2002","unstructured":"Bohm, W., Hammes, J., Draper, B., Chawathe, M., Ross, C., Rinker, R., Najjar, W.: Mapping a single assignment programming language to reconfigurable systems. Journal of Supercomputing\u00a021(2), 117\u2013130 (2002)","journal-title":"Journal of Supercomputing"},{"key":"11_CR14","unstructured":"Bormans, J., Denolf, K., Wuytack, S., Nachtergaele, L., Bolsens, I.: Integrating system-level low power methodologies into a real-life design flow. In: PATMOS, pp. 19\u201328 (1999)"},{"key":"11_CR15","doi-asserted-by":"crossref","unstructured":"Cohen, A., Girbal, S., Parello, D., Sigler, M., Temam, O., Vasilache, N.: Facilitating the search for compositions of program transformations. In: ICS, June 2005, pp. 151\u2013160 (2005)","DOI":"10.1145\/1088149.1088169"},{"issue":"4","key":"11_CR16","doi-asserted-by":"publisher","first-page":"41","DOI":"10.1109\/2.839320","volume":"33","author":"A. DeHon","year":"2000","unstructured":"DeHon, A.: The density advantage of configurable computing. IEEE Computer\u00a033(4), 41\u201349 (2000)","journal-title":"IEEE Computer"},{"key":"11_CR17","unstructured":"Devos, H., Eeckhaut, H., Schrauwen, B., Christiaens, M., Stroobandt, D.: Ever considered SystemC? In: ProRISC Workshop, pp. 358\u2013363 (2004)"},{"key":"11_CR18","doi-asserted-by":"crossref","unstructured":"Fursin, G.: Iterative Compilation and Performance Prediction for Numerical Applications. PhD thesis, University of Edinburgh (2004)","DOI":"10.1007\/11596110_24"},{"key":"11_CR19","unstructured":"Girbal, S.: Optimisation d\u2019applications - Composition de transformations de programme: mod\u00e8le et outils. PhD thesis, l\u2019Universit\u00e9 de Paris XI Orsay (2005)"},{"key":"11_CR20","unstructured":"Guillou, A.C., Quinton, P., Risset, T.: Hardware synthesis for systems of recurrence equations with multi-dimensional schedule. International Journal of Embedded Systems (to appear, 2005)"},{"issue":"1\/2","key":"11_CR21","doi-asserted-by":"publisher","first-page":"114","DOI":"10.1504\/IJES.2006.010170","volume":"2","author":"F. Hannig","year":"2006","unstructured":"Hannig, F., Dutta, H., Teich, J.: Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: Architectural parameters and methodology. International Journal of Embedded Systems\u00a02(1\/2), 114\u2013127 (2006)","journal-title":"International Journal of Embedded Systems"},{"issue":"4","key":"11_CR22","doi-asserted-by":"publisher","first-page":"1575","DOI":"10.1109\/TSP.2005.843704","volume":"53","author":"C.-T. Huang","year":"2005","unstructured":"Huang, C.-T., Tseng, P.-C., Chen, L.-G.: Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform. IEEE Transactions on Signal Processing\u00a053(4), 1575\u20131586 (2005)","journal-title":"IEEE Transactions on Signal Processing"},{"key":"11_CR23","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1007\/3-540-45874-3_10","volume-title":"Embedded Processor Design Challenges","author":"P.M.W. Knijnenburg","year":"2002","unstructured":"Knijnenburg, P.M.W., Kisuki, T., O\u2019Boyle, M.F.P.: Iterative compilation. In: Deprettere, F., Teich, J., Vassiliadis, S. (eds.) Embedded Processor Design Challenges. LNCS, vol.\u00a02268, pp. 171\u2013187. Springer, Heidelberg (2002)"},{"issue":"7","key":"11_CR24","doi-asserted-by":"publisher","first-page":"674","DOI":"10.1109\/34.192463","volume":"11","author":"S.G. Mallat","year":"1989","unstructured":"Mallat, S.G.: A theory for multiresolution signal decomposition: the wavelet representation. IEEE Transactions on Pattern Analysis and Machine Intelligence\u00a011(7), 674\u2013693 (1989)","journal-title":"IEEE Transactions on Pattern Analysis and Machine Intelligence"},{"key":"11_CR25","doi-asserted-by":"crossref","unstructured":"Martonosi, M., Gupta, A., Anderson, T.E.: Tuning memory performance of sequential and parallel programs. IEEE Computer (April 1995)","DOI":"10.1109\/2.375175"},{"issue":"4","key":"11_CR26","doi-asserted-by":"publisher","first-page":"424","DOI":"10.1145\/233561.233564","volume":"18","author":"K.S. McKinley","year":"1996","unstructured":"McKinley, K.S., Carr, S., Tseng, C.-W.: Improving data locality with loop transformations. ACM Transactions on Programming Languages and Systems\u00a018(4), 424\u2013453 (1996), http:\/\/www.acm.org\/pubs\/toc\/Abstracts\/toplas\/233564.html","journal-title":"ACM Transactions on Programming Languages and Systems"},{"issue":"4","key":"11_CR27","doi-asserted-by":"publisher","first-page":"75","DOI":"10.1109\/2.917544","volume":"34","author":"B.R. Rau","year":"2001","unstructured":"Rau, B.R., Schlansker, M.S.: Embedded computer architecture and automation. IEEE Computer\u00a034(4), 75\u201383 (2001)","journal-title":"IEEE Computer"},{"key":"11_CR28","doi-asserted-by":"crossref","unstructured":"Turjan, A., Kienhuis, B., Deprettere, E.: Translating affine nested-loop programs to process networks. In: CASES (2004), http:\/\/www.liacs.nl\/~aturjan\/publications.html","DOI":"10.1145\/1023833.1023864"},{"key":"11_CR29","doi-asserted-by":"crossref","unstructured":"Wolf, M.E., Lam, M.S.: A data locality optimizing algorithm. In: PLDI. SIGPLAN Notices, vol.\u00a026, pp. 30\u201344 (1991), http:\/\/suif.stanford.edu\/papers\/wolf91a.ps","DOI":"10.1145\/113446.113449"},{"key":"11_CR30","doi-asserted-by":"crossref","unstructured":"Wolfe, M.: Experiences with data dependence abstractions. In: ICS, Cologne, West Germany, pp. 321\u2013329 (1991), doi:10.1145\/109025.109104","DOI":"10.1145\/109025.109104"},{"key":"11_CR31","doi-asserted-by":"publisher","first-page":"163","DOI":"10.1006\/jvlc.2000.0191","volume":"12","author":"Y. Yu","year":"2001","unstructured":"Yu, Y., D\u2019Hollander, E.H.: Loop parallelization using the 3D iteration space visualizer. Journal of Visual Languages and Computing\u00a012, 163\u2013181 (2001)","journal-title":"Journal of Visual Languages and Computing"},{"issue":"12","key":"11_CR32","doi-asserted-by":"publisher","first-page":"1246","DOI":"10.1109\/76.974679","volume":"11","author":"N.D. Zervas","year":"2001","unstructured":"Zervas, N.D., Anagnostopoulos, G.P., Spiliotopoulos, V., Andreopoulos, Y., Goutis, C.E.: Evaluation of design alternatives for the 2D-discrete wavelet transform. IEEE Transactions on Circuits and Systems for Video Technology\u00a011(12), 1246\u20131262 (2001)","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"11_CR33","doi-asserted-by":"crossref","unstructured":"Zissulescu, C., Kienhuis, B., Deprettere, E.: Expression synthesis in process networks generated by LAURA. In: ASAP, July 2005, pp. 15\u201321 (2005)","DOI":"10.1109\/ASAP.2005.34"}],"container-title":["Lecture Notes in Computer Science","Transactions on High-Performance Embedded Architectures and Compilers I"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-71528-3_11","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,13]],"date-time":"2023-05-13T13:44:41Z","timestamp":1683985481000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-71528-3_11"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"ISBN":["9783540715276","9783540715283"],"references-count":33,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-71528-3_11","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2007]]}}}