{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,13]],"date-time":"2025-05-13T11:05:30Z","timestamp":1747134330148},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540725206"},{"type":"electronic","value":"9783540725213"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-72521-3_20","type":"book-chapter","created":{"date-parts":[[2007,6,10]],"date-time":"2007-06-10T12:53:29Z","timestamp":1181480009000},"page":"267-282","source":"Crossref","is-referenced-by-count":5,"title":["Optimal Bitwise Register Allocation Using Integer Linear Programming"],"prefix":"10.1007","author":[{"given":"Rajkishore","family":"Barik","sequence":"first","affiliation":[]},{"given":"Christian","family":"Grothoff","sequence":"additional","affiliation":[]},{"given":"Rahul","family":"Gupta","sequence":"additional","affiliation":[]},{"given":"Vinayaka","family":"Pandit","sequence":"additional","affiliation":[]},{"given":"Raghavendra","family":"Udupa","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"20_CR1","unstructured":"http:\/\/gcc.gnu.org\/ (2004)"},{"key":"20_CR2","doi-asserted-by":"publisher","first-page":"243","DOI":"10.1145\/378795.378854","volume-title":"Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation","author":"A.W. Appel","year":"2001","unstructured":"Appel, A.W., George, L.: Optimal spilling for cisc machines with few registers. In: Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation, pp. 243\u2013253. ACM Press, New York (2001)"},{"key":"20_CR3","first-page":"311","volume-title":"Proceedings of the Conference on Programming Language Design and Implementation (PLDI), vol. 27","author":"P. Briggs","year":"1992","unstructured":"Briggs, P., Cooper, K.D., Torczon, L.: Rematerialization. In: Proceedings of the Conference on Programming Language Design and Implementation (PLDI), vol. 27, pp. 311\u2013321. ACM Press, New York (1992), citeseer.ist.psu.edu\/briggs92rematerialization.html"},{"issue":"3","key":"20_CR4","doi-asserted-by":"publisher","first-page":"428","DOI":"10.1145\/177492.177575","volume":"16","author":"P. Briggs","year":"1994","unstructured":"Briggs, P., Cooper, K.D., Torczon, L.: Improvements to graph coloring register allocation. ACM Transactions on Programming Languages and Systems\u00a016(3), 428\u2013455 (1994), citeseer.ist.psu.edu\/briggs94improvements.html","journal-title":"ACM Transactions on Programming Languages and Systems"},{"key":"20_CR5","doi-asserted-by":"publisher","first-page":"98","DOI":"10.1145\/800230.806984","volume-title":"Proceedings of the ACM SIGPLAN \u201982 Symposium on Compiler Construction","author":"G.J. Chaitin","year":"1982","unstructured":"Chaitin, G.J.: Register allocation and spilling via graph coloring. In: Proceedings of the ACM SIGPLAN \u201982 Symposium on Compiler Construction, Jun. 1982, pp. 98\u2013105. ACM Press, New York (1982)"},{"key":"20_CR6","doi-asserted-by":"publisher","first-page":"47","DOI":"10.1016\/0096-0551(81)90048-5","volume":"6","author":"G.J. Chaitin","year":"1981","unstructured":"Chaitin, G.J., et al.: Register allocation via coloring. Computer Languages\u00a06, 47\u201357 (1981)","journal-title":"Computer Languages"},{"key":"20_CR7","first-page":"245","volume-title":"MICRO 35: Proceedings of the 35th annual ACM\/IEEE international symposium on Microarchitecture","author":"C. Fu","year":"2002","unstructured":"Fu, C., Wilken, K.: A faster optimal register allocator. In: MICRO 35: Proceedings of the 35th annual ACM\/IEEE international symposium on Microarchitecture, Istanbul, Turkey, pp. 245\u2013256. IEEE Computer Society Press, Los Alamitos (2002)"},{"issue":"3","key":"20_CR8","doi-asserted-by":"publisher","first-page":"300","DOI":"10.1145\/229542.229546","volume":"18","author":"L. George","year":"1996","unstructured":"George, L., Appel, A.W.: Iterated register coalescing. ACM Transactions on Programming Languages and Systems\u00a018(3), 300\u2013324 (1996), citeseer.ist.psu.edu\/george96iterated.html","journal-title":"ACM Transactions on Programming Languages and Systems"},{"key":"20_CR9","doi-asserted-by":"crossref","unstructured":"Goodwin, D.W., Wilken, K.D.: Optimal and Near-Optimal Global Register Allocation Using 0-1 Integer Programming (1996)","DOI":"10.1002\/(SICI)1097-024X(199608)26:8<929::AID-SPE40>3.3.CO;2-K"},{"key":"20_CR10","unstructured":"Lee, C., Potkonjak, M., Mangione-Smith, W.H.: Mediabench: A tool for evaluating and synthesizing multimedia and communicatons systems. In: International Symposium on Microarchitecture (1997)"},{"key":"20_CR11","doi-asserted-by":"publisher","first-page":"69","DOI":"10.1145\/581630.581642","volume-title":"Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems","author":"B. Li","year":"2002","unstructured":"Li, B., Gupta, R.: Bit section instruction set extension of arm for embedded applications. In: Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems, pp. 69\u201378. ACM Press, New York (2002)"},{"key":"20_CR12","series-title":"Lecture Notes in Computer Science","volume-title":"Languages and Compilers for High Performance Computing","author":"B. Li","year":"2005","unstructured":"Li, B., Zhang, Y., Gupta, R.: Speculative subword register allocation in embedded processors. In: Eigenmann, R., Li, Z., Midkiff, S.P. (eds.) LCPC 2004. LNCS, vol.\u00a03602, Springer, Heidelberg (2005)"},{"key":"20_CR13","volume-title":"Computer Solution of Linear Programs","author":"J.L. Nazareth","year":"1987","unstructured":"Nazareth, J.L.: Computer Solution of Linear Programs. Oxford University Press, Oxford (1987)"},{"key":"20_CR14","first-page":"196","volume-title":"International Conference on Parallel Architectures and Compilation Techniques","author":"J. Park","year":"1998","unstructured":"Park, J., Moon, S.-M.: Optimistic register coalescing. In: Gaudiot, J.-L. (ed.) International Conference on Parallel Architectures and Compilation Techniques, Paris, October 1998, pp. 196\u2013204. North-Holland, Amsterdam (1998)"},{"issue":"5","key":"20_CR15","doi-asserted-by":"publisher","first-page":"895","DOI":"10.1145\/330249.330250","volume":"21","author":"M. Poletto","year":"1999","unstructured":"Poletto, M., Sarkar, V.: Linear scan register allocation. ACM Transactions on Programming Languages and Systems\u00a021(5), 895\u2013913 (1999), citeseer.ist.psu.edu\/poletto99linear.html","journal-title":"ACM Transactions on Programming Languages and Systems"},{"key":"20_CR16","unstructured":"Stephenson, M., Babb, J., Amarasinghe, S.: Bitwidth analysis with application to silicon compilation. http:\/\/cag.lcs.mit.edu\/commit\/papers\/00\/bitwise-pldi2k.pdf"},{"issue":"1","key":"20_CR17","doi-asserted-by":"publisher","first-page":"85","DOI":"10.1145\/640128.604139","volume":"38","author":"S. Tallam","year":"2003","unstructured":"Tallam, S., Gupta, R.: Bitwidth aware global register allocation. ACM SIGPLAN Notices\u00a038(1), 85\u201396 (2003)","journal-title":"ACM SIGPLAN Notices"}],"container-title":["Lecture Notes in Computer Science","Languages and Compilers for Parallel Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-72521-3_20.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,19]],"date-time":"2020-11-19T00:34:15Z","timestamp":1605746055000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-72521-3_20"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540725206","9783540725213"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-72521-3_20","relation":{},"subject":[]}}