{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T04:57:49Z","timestamp":1777438669860,"version":"3.51.4"},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540726845","type":"print"},{"value":"9783540726852","type":"electronic"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-72685-2_12","type":"book-chapter","created":{"date-parts":[[2007,6,30]],"date-time":"2007-06-30T01:31:29Z","timestamp":1183167089000},"page":"121-132","source":"Crossref","is-referenced-by-count":6,"title":["A Design Method for Heterogeneous Adders"],"prefix":"10.1007","author":[{"given":"Jeong-Gun","family":"Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeong-A","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Byeong-Seok","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Milos D.","family":"Ercegovac","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"12_CR1","doi-asserted-by":"publisher","first-page":"689","DOI":"10.1109\/82.539001","volume":"43","author":"C. Nagendra","year":"1996","unstructured":"Nagendra, C., Irwin, M.J., Owens, R.M.: Area-time-power tradeoffs in parallel adders. IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing\u00a043, 689\u2013702 (1996)","journal-title":"IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing"},{"key":"12_CR2","doi-asserted-by":"crossref","unstructured":"Oklobdzija, V., Zeydel, B., Mathew, S., Krishnamurthy, R.: Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. In: Proc. IEEE Symposium on Computer Arithmetic, Jun. 2003, pp. 272\u2013279 (2003)","DOI":"10.1109\/ARITH.2003.1207688"},{"key":"12_CR3","doi-asserted-by":"crossref","unstructured":"Wang, Y., Pai, C., Song, X.: The design of hybrid carry-lookahead\/carry-select adders. IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing\u00a049 (2002)","DOI":"10.1109\/82.996053"},{"issue":"2","key":"12_CR4","doi-asserted-by":"publisher","first-page":"292","DOI":"10.1109\/92.386228","volume":"3","author":"V. Oklobdzija","year":"1995","unstructured":"Oklobdzija, V., Villeger, D.: Improving Multiplier Design by Using Column Compression Tree and Optimized Final Adder in CMOS Technology. IEEE Trans. on VLSI\u00a03(2), 292\u2013301 (1995)","journal-title":"IEEE Trans. on VLSI"},{"issue":"3","key":"12_CR5","doi-asserted-by":"publisher","first-page":"321","DOI":"10.1007\/BF00929625","volume":"14","author":"P.F. Stelling","year":"1996","unstructured":"Stelling, P.F., Oklobdzija, V.: Design Strategies for Optimal Hybrid Final Adders in a Parallel Multiplier. Journal of VLSI Signal Processing\u00a014(3), 321\u2013331 (1996)","journal-title":"Journal of VLSI Signal Processing"},{"key":"12_CR6","volume-title":"Digital Arithmetic","author":"M.D. Ercegovac","year":"2004","unstructured":"Ercegovac, M.D., Lang, T.: Digital Arithmetic. Morgan Kaufmann, San Francisco (2004)"},{"key":"12_CR7","unstructured":"Zimmermann, R.: Binary Adder Architectures for Cell-Based VLSI and their Synthesis. PhD thesis, Swiss Federal Institute of Technology (ETH) Zurich, Hartung-Gorre Verlag (1998)"},{"key":"12_CR8","doi-asserted-by":"crossref","unstructured":"Knowles, S.: A Family of Adders. In: Proc. IEEE Symposium on Computer Arithmetic, pp. 30\u201334 (1999)","DOI":"10.1109\/ARITH.1999.762825"},{"key":"12_CR9","volume-title":"Model Building in Mathematical Programming","author":"H.P. Williams","year":"1999","unstructured":"Williams, H.P.: Model Building in Mathematical Programming, 4th edn. John Wiley, New York (1999)","edition":"4"},{"key":"12_CR10","unstructured":"Berkelaar, M.: lp_solve - version 4.0. Eindhoven University of Technology (2003), \n                    \n                      ftp:\/\/ftp.ics.ele.tue.nl\/pub\/lp_solve\/"},{"key":"12_CR11","unstructured":"IDEC-C221: IDEC Cell Library Data Book. IC Design Education Center (2000)"},{"key":"12_CR12","unstructured":"DesignWare IP Family Reference Guide. Synopsis Corporation, September 12 (2005)"}],"container-title":["Lecture Notes in Computer Science","Embedded Software and Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-72685-2_12.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,19]],"date-time":"2020-11-19T05:03:33Z","timestamp":1605762213000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-72685-2_12"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540726845","9783540726852"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-72685-2_12","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[]}}