{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:54:51Z","timestamp":1725490491055},"publisher-location":"Berlin, Heidelberg","reference-count":17,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540736226"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-73625-7_18","type":"book-chapter","created":{"date-parts":[[2007,8,29]],"date-time":"2007-08-29T12:49:21Z","timestamp":1188391761000},"page":"159-168","source":"Crossref","is-referenced-by-count":12,"title":["MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing"],"prefix":"10.1007","author":[{"given":"Marco","family":"Lanuzza","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefania","family":"Perri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pasquale","family":"Corsonello","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"18_CR1","doi-asserted-by":"crossref","unstructured":"Hartenstein, R.: A Decade of Reconfigurable Computing: a Visionary Retrospective. In: Proc. of Design, Automation and Test in Europe (DATE), pp. 642\u2013649, March 13-16, 2001 Munich, Germany (2001)","DOI":"10.1109\/DATE.2001.915091"},{"key":"18_CR2","doi-asserted-by":"crossref","unstructured":"Ristimaki, T., Nurmi, J.: Reconfigurable IP blocks: a survey. In: Proc. of Int. Symp. on System-on-Chip (SoC), pp. 117\u2013122, November 16-18, 2004 Tampere, Finland (2004)","DOI":"10.1109\/ISSOC.2004.1411163"},{"key":"18_CR3","doi-asserted-by":"crossref","unstructured":"Marshall, A., Stansfield, T., Kostarnov, I., Vuillemin, J., Hutchings, B.: A reconfigurable arithmetic array for multimedia applications. In: Proc. of Int. Symp. on Field-Programmable Gate Arrays (FPGA), pp. 135\u2013143, February 21-23, 1999 Monterey, California, USA (1999)","DOI":"10.1145\/296399.296444"},{"key":"18_CR4","doi-asserted-by":"crossref","unstructured":"Schmit, H., Whelihan, D., Tsai, A., Moe, M., Levine, B., Taylor, R R.: PipeRench: A virtualized programmable datapath in 0.18 micron technology. In: Proc. of the IEEE Conf. on Custom Integrated Circuits (CICC), pp. 63\u201366, May 12-15, 2002 Orlando, Florida, USA (2002)","DOI":"10.1109\/CICC.2002.1012767"},{"key":"18_CR5","doi-asserted-by":"crossref","unstructured":"Cronquist, D.C., Fisher, C., Figueroa, M., Franklin, P., Ebeling, C.: Architecture design of reconfigurable pipelined datapaths. In: Proc. of 20th Anniversary Conf. on Advanced Research in VLSI (ARVLSI), pp. 23\u201340, March 21-24, 1999, Atlanta, Georgia, USA (1999)","DOI":"10.1109\/ARVLSI.1999.756035"},{"issue":"5","key":"18_CR6","doi-asserted-by":"publisher","first-page":"465","DOI":"10.1109\/12.859540","volume":"49","author":"H. Singh","year":"2000","unstructured":"Singh, H., Lee, M.-H., Lu, G., Kurdahi, F.J., Bagherzadeh, N., Filho, C.: MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Transactions on Computers\u00a049(5), 465\u2013481 (2000)","journal-title":"IEEE Transactions on Computers"},{"key":"18_CR7","doi-asserted-by":"crossref","unstructured":"Mirsky, E., DeHon, A.: MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources. In: Proc. of the IEEE Symp. on FPGAs for Custom-Computing Machines (FCCM), Napa, California, USA, April 17-19, 1996, pp. 157\u2013166 (1996)","DOI":"10.1109\/FPGA.1996.564808"},{"key":"18_CR8","doi-asserted-by":"crossref","unstructured":"Miyamori, T., Olukotun, K.: A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. In: Proc. of the IEEE Symp. On FPGAs for Custom-Computing Machines (FCCM), Napa, California, USA, April 14-17, 1998, pp. 2\u201311 (1998)","DOI":"10.1109\/FPGA.1998.707876"},{"key":"18_CR9","doi-asserted-by":"crossref","unstructured":"Veredas, F.J., Scheppler, M., Moffat, W., Bingfeng, M.: Custom implementation of the coarse-grained reconfigurable ADRES architecture for multimedia purposes. In: Proc. of 15th Int. Conf. on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 24\u201326 (2005)","DOI":"10.1109\/FPL.2005.1515707"},{"key":"18_CR10","unstructured":"Elixent Ltd. \n                    \n                      http:\/\/www.elixent.com"},{"key":"18_CR11","unstructured":"Motomura, M., Dynamically, A.: Reconfigurable Processor Architecture, Microprocessor Forum, October 10, 2002, California, USA (2002)"},{"issue":"2","key":"18_CR12","doi-asserted-by":"publisher","first-page":"167","DOI":"10.1023\/A:1024499601571","volume":"26","author":"V. Baumgarte","year":"2003","unstructured":"Baumgarte, V., Ehlers, G., May, F., Nuckel, A., Vorbach, M., Weinhardt, M.: PCT-XPP A Self-Reconfigurable Data Processing Architecture. The Journal of Supercomputing\u00a026(2), 167\u2013184 (2003)","journal-title":"The Journal of Supercomputing"},{"key":"18_CR13","unstructured":"MathStar\n                    TM\n                  , \n                    \n                      http:\/\/www.mathstar.com\/products.html"},{"key":"18_CR14","doi-asserted-by":"crossref","unstructured":"Lanuzza, M., Perri, S., Margala, M., Corsonello, P.: Low-cost fully reconfigurable data-path for FPGA-based multimedia processor. In: Proc. of 15th Int. Conf. on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005, pp. 13\u201318 (2005)","DOI":"10.1109\/FPL.2005.1515692"},{"key":"18_CR15","doi-asserted-by":"crossref","unstructured":"Lanuzza, M., Margala, M., Corsonello, P.: Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. In: Proc. of Int.l Symp. on Low Power Electronics and Design (ISLPED), San Diego, California, USA, August 8-10, 2005, pp. 161\u2013166 (2005)","DOI":"10.1145\/1077603.1077645"},{"key":"18_CR16","unstructured":"Virtex-4 User Guide, \n                    \n                      http:\/\/www.xilinx.com"},{"issue":"11","key":"18_CR17","doi-asserted-by":"publisher","first-page":"1436","DOI":"10.1109\/TC.2004.98","volume":"53","author":"C. Ebeling","year":"2004","unstructured":"Ebeling, C., Fisher, C., Guanbin, X., Manyuan, S., Liu, H.: Implementing an OFDM receiver on the RaPiD reconfigurable architecture. IEEE Transactions on Computers\u00a053(11), 1436\u20131448 (2004)","journal-title":"IEEE Transactions on Computers"}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-73625-7_18.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T09:54:22Z","timestamp":1619517262000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-73625-7_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540736226"],"references-count":17,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-73625-7_18","relation":{},"subject":[]}}