{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:55:05Z","timestamp":1725490505098},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540736226"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-73625-7_29","type":"book-chapter","created":{"date-parts":[[2007,8,29]],"date-time":"2007-08-29T08:49:21Z","timestamp":1188377361000},"page":"273-282","source":"Crossref","is-referenced-by-count":3,"title":["Parallel Memory Architecture for TTA Processor"],"prefix":"10.1007","author":[{"given":"Jarno K.","family":"Tanskanen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Teemu","family":"Pitk\u00e4nen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Risto","family":"M\u00e4kinen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jarmo","family":"Takala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"29_CR1","volume-title":"Microprocessor Architectures: From VLIW to TTA","author":"H. Corporaal","year":"1997","unstructured":"Corporaal, H.: Microprocessor Architectures: From VLIW to TTA. John Wiley & Sons, Chichester, UK (1997)"},{"key":"29_CR2","doi-asserted-by":"crossref","unstructured":"Sohi, G.S., Franklin, M.: High-bandwidth data memory systems for superscalar processors. In: Proc. 4th Int. Conf. Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA, U.S.A., pp. 53\u201362 (April 8-11, 1991)","DOI":"10.1145\/106972.106980"},{"key":"29_CR3","doi-asserted-by":"crossref","unstructured":"Juan, T., Navarro, J.J., Temam, O.: Data caches for superscalar processors. In: Proc. 11th Int. Conf. Supercomputing, Vienna, Austria, pp. 60\u201367 (July 7-11, 1997)","DOI":"10.1145\/263580.263595"},{"key":"29_CR4","doi-asserted-by":"crossref","first-page":"46","DOI":"10.1109\/MICRO.1997.645796","volume-title":"Proc. 30th Ann. ACM\/IEEE Int. Symp. Microarchitecture","author":"J.A. Rivers","year":"1997","unstructured":"Rivers, J.A., Tyson, G.S., Davidson, E.S., Austin, T.M.: On high-bandwidth data cache design for multi-issue processors. In: Proc. 30th Ann. ACM\/IEEE Int. Symp. Microarchitecture, pp. 46\u201356. Research Triangle Park, NC, U.S.A (December 1-3, 1997)"},{"key":"29_CR5","unstructured":"Sawyer, N., Defossez, M.: Quad-port memories in Virtex devices. Xilinx application note, XAPP228 (v1.0) (September 24, 2002)"},{"key":"29_CR6","doi-asserted-by":"crossref","unstructured":"Zhu, Z., Johguchi, K., Mattausch, H.J., Koide, T., Hirakawa, T., Hironaka, T.: A novel hierarchical multi-port cache. In: Proc. 29th European Solid-State Circuits Conf., Estoril, Portugal, pp. 405\u2013408 (September 16-18, 2003)","DOI":"10.1109\/ESSCIRC.2003.1257158"},{"key":"29_CR7","first-page":"361","volume-title":"Proc. IEEE Int. Symp. Circuits and Systems","author":"K. Patel","year":"2004","unstructured":"Patel, K., Macii, E., Poncino, M.: Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip. In: Proc. IEEE Int. Symp. Circuits and Systems, Vancouver, British Columbia, Canada, May 23-26, 2004, vol.\u00a02, pp. 361\u2013364. IEEE Computer Society Press, Los Alamitos (2004)"},{"key":"29_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"205","DOI":"10.1007\/11802839_29","volume-title":"Reconfigurable Computing: Architectures and Applications","author":"S.S. Ang","year":"2006","unstructured":"Ang, S.S., Constantinides, G., Cheung, P., Luk, W.: A flexible multi-port caching scheme for reconfigurable platforms. In: Bertels, K., Cardoso, J.M.P., Vassiliadis, S. (eds.) ARC 2006. LNCS, vol.\u00a03985, pp. 205\u2013216. Springer, Heidelberg (2006)"},{"key":"29_CR9","first-page":"524","volume-title":"Proc. IEEE Int. Symp. Circuits and Systems","author":"J.H. Takala","year":"2003","unstructured":"Takala, J.H., J\u00e4rvinen, T.S., Sorokin, H.T.: Conflict-free parallel memory access scheme for FFT processors. In: Proc. IEEE Int. Symp. Circuits and Systems, Bangkok, Thailand, May 25-28, 2003, vol.\u00a04, pp. 524\u2013527. IEEE Computer Society Press, Los Alamitos (2003)"},{"key":"29_CR10","doi-asserted-by":"crossref","unstructured":"J\u00e4\u00e4skel\u00e4inen, P., Guzma, V., Cilio, A., Takala, J.: Codesign toolset for application-specific instruction-set processors. In: Proc. SPIE - Multimedia on Mobile Devices (2007)","DOI":"10.1117\/12.707233"},{"key":"29_CR11","unstructured":"M\u00e4kinen, R.: Fast Fourier transform on transport triggered architectures. M.Sc. Thesis, Tampere University of Technology, Tampere, Finland (October 2005)"},{"key":"29_CR12","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"227","DOI":"10.1007\/11796435_24","volume-title":"Embedded Computer Systems: Architectures, Modeling, and Simulation","author":"T. Pitk\u00e4nen","year":"2006","unstructured":"Pitk\u00e4nen, T., M\u00e4kinen, R., Heikkinen, J., Partanen, T., Takala, J.: Low-power, high-performance TTA processor for 1024-point Fast Fourier transform. In: Vassiliadis, S., Wong, S., H\u00e4m\u00e4l\u00e4inen, T.D. (eds.) SAMOS 2006. LNCS, vol.\u00a04017, pp. 227\u2013236. Springer, Heidelberg (2006)"},{"issue":"12","key":"29_CR13","doi-asserted-by":"publisher","first-page":"1566","DOI":"10.1109\/T-C.1971.223171","volume":"C-20","author":"P. Budnik","year":"1971","unstructured":"Budnik, P., Kuck, D.J.: The organization and use of parallel memories. IEEE Trans. Comput.\u00a0C-20(12), 1566\u20131569 (1971)","journal-title":"IEEE Trans. Comput."},{"issue":"4","key":"29_CR14","doi-asserted-by":"publisher","first-page":"361","DOI":"10.1109\/71.219753","volume":"4","author":"K. Kim","year":"1993","unstructured":"Kim, K., Prasanna, V.K.: Latin squares for parallel array access. IEEE Trans. Parallel and Distrib. Syst.\u00a04(4), 361\u2013370 (1993)","journal-title":"IEEE Trans. Parallel and Distrib. Syst."},{"key":"29_CR15","unstructured":"Frailong, J.M., Jalby, W., Lenfant, J.: XOR-schemes: a flexible data organization in parallel memories. In: Proc. Int. Conf. Parallel Processing, pp. 276\u2013283 (August 20-23, 1985)"},{"issue":"2","key":"29_CR16","doi-asserted-by":"publisher","first-page":"162","DOI":"10.1006\/jpdc.1995.1038","volume":"25","author":"Z. Liu","year":"1995","unstructured":"Liu, Z., Li, X.: XOR storage schemes for frequently used data patterns. Journal of Parallel and Distributed Computing\u00a025(2), 162\u2013173 (1995)","journal-title":"Journal of Parallel and Distributed Computing"},{"issue":"6","key":"29_CR17","doi-asserted-by":"publisher","first-page":"595","DOI":"10.1109\/71.506698","volume":"7","author":"A. Deb","year":"1996","unstructured":"Deb, A.: Multiskewing \u2013 a novel technique for optimal parallel memory access. IEEE Trans. Parallel and Distrib. Syst.\u00a07(6), 595\u2013604 (1996)","journal-title":"IEEE Trans. Parallel and Distrib. Syst."},{"key":"29_CR18","doi-asserted-by":"crossref","unstructured":"Rau, B.R.: Pseudo-randomly interleaved memory. In: Proc. 18th Ann. Int. Symp. Computer Architecture, Toronto, Ontario, Canada, pp. 74\u201383 (May 27-30, 1991)","DOI":"10.1145\/115952.115961"},{"issue":"2","key":"29_CR19","doi-asserted-by":"publisher","first-page":"248","DOI":"10.1006\/jpdc.1995.1063","volume":"26","author":"A. Seznec","year":"1995","unstructured":"Seznec, A., Lenfant, J.: Odd memory systems: a new approach. Journal of Parallel and Distributed Computing\u00a026(2), 248\u2013256 (1995)","journal-title":"Journal of Parallel and Distributed Computing"},{"issue":"2","key":"29_CR20","doi-asserted-by":"publisher","first-page":"215","DOI":"10.1007\/s11265-005-4962-2","volume":"40","author":"J.K. Tanskanen","year":"2005","unstructured":"Tanskanen, J.K., Creutzburg, R., Niittylahti, J.T.: On design of parallel memory access schemes for video coding. J. VLSI Signal Processing\u00a040(2), 215\u2013237 (2005)","journal-title":"J. VLSI Signal Processing"}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-73625-7_29.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T05:54:28Z","timestamp":1619502868000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-73625-7_29"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540736226"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-73625-7_29","relation":{},"subject":[]}}