{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:54:48Z","timestamp":1725490488882},"publisher-location":"Berlin, Heidelberg","reference-count":26,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540736226"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-73625-7_45","type":"book-chapter","created":{"date-parts":[[2007,8,29]],"date-time":"2007-08-29T12:49:21Z","timestamp":1188391761000},"page":"443-453","source":"Crossref","is-referenced-by-count":5,"title":["Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks"],"prefix":"10.1007","author":[{"given":"Panu","family":"H\u00e4m\u00e4l\u00e4inen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marko","family":"H\u00e4nnik\u00e4inen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Timo D.","family":"H\u00e4m\u00e4l\u00e4inen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"7","key":"45_CR1","doi-asserted-by":"publisher","first-page":"1002","DOI":"10.1109\/JPROC.2003.814620","volume":"91","author":"J.A. Stankovic","year":"2003","unstructured":"Stankovic, J.A., Abdelzaher, T.F., Lu, C., Sha, L., Hou, J.C.: Real-time communication and coordination in embedded sensor networks. Proceedings of the IEEE\u00a091(7), 1002\u20131022 (2003)","journal-title":"Proceedings of the IEEE"},{"key":"45_CR2","unstructured":"H\u00e4m\u00e4l\u00e4inen, P., Kuorilehto, M., Alho, T., H\u00e4nnik\u00e4inen, M., H\u00e4m\u00e4l\u00e4inen, T.D.: Security in wireless sensor networks: Considerations and experiments. In: Proc. Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VI) Workshop\u2013Special Session on Wireless Sensor Networks, Samos, Greece, pp. 167\u2013177 (July 17-20, 2006)"},{"key":"45_CR3","unstructured":"ZigBee Alliance: ZigBee Specification Version 1.0 (December 2004)"},{"key":"45_CR4","doi-asserted-by":"crossref","unstructured":"Suhonen, J., Kohvakka, M., H\u00e4nnik\u00e4inen, M., H\u00e4m\u00e4l\u00e4inen, T.D.: Design, implementation, and experiments on outdoor deployment of wireless sensor network for environmental monitoring. In: Proc. Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VI) Workshop\u2013Special Session on Wireless Sensor Networks, Samos, Greece, pp. 109\u2013121 (July 17-20, 2006)","DOI":"10.1007\/11796435_13"},{"key":"45_CR5","first-page":"253","volume-title":"Wireless Sensor Networks","author":"S. Avancha","year":"2004","unstructured":"Avancha, S., Undercoffer, J., Joshi, A., Pinkston, J.: Security for Wireless Sensor Networks. In: Wireless Sensor Networks, 1st edn. pp. 253\u2013275. Springer, Heidelberg (2004)","edition":"1"},{"key":"45_CR6","unstructured":"National Institute of Standards and Technology (NIST): Advanced Encryption Standard (AES), FIPS-197 (2001)"},{"key":"45_CR7","unstructured":"IEEE: IEEE Standard for Local and Metropolitan Area Networks\u2014Part 15.4: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPAN), IEEE Std 802.15.4 (2003)"},{"key":"45_CR8","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"239","DOI":"10.1007\/3-540-45682-1_15","volume-title":"Advances in Cryptology - ASIACRYPT 2001","author":"A. Satoh","year":"2001","unstructured":"Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A compact Rijndael hardware architecture with S-box optimization. In: Boyd, C. (ed.) ASIACRYPT 2001. LNCS, vol.\u00a02248, pp. 239\u2013254. Springer, Heidelberg (2001)"},{"key":"45_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"427","DOI":"10.1007\/11545262_31","volume-title":"Cryptographic Hardware and Embedded Systems \u2013 CHES 2005","author":"T. Good","year":"2005","unstructured":"Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol.\u00a03659, pp. 427\u2013440. Springer, Heidelberg (2005)"},{"key":"45_CR10","doi-asserted-by":"crossref","unstructured":"Pramstaller, N., Mangard, S., Dominikus, S., Wolkerstorfer, J.: Efficient AES implementations on ASICs and FPGAs. In: Proc. 4th Conf. on the Advanced Encryption Standard (AES 2004), Bonn, Germany, May 10-12, 2005, pp. 98\u2013112 (2005)","DOI":"10.1007\/11506447_9"},{"key":"45_CR11","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"357","DOI":"10.1007\/978-3-540-28632-5_26","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2004","author":"M. Feldhofer","year":"2004","unstructured":"Feldhofer, M., Dominikus, S., Wolkerstorfer, J.: Strong authentication for RFID systems using the AES algorithm. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol.\u00a03156, pp. 357\u2013370. Springer, Heidelberg (2004)"},{"issue":"1","key":"45_CR12","doi-asserted-by":"publisher","first-page":"13","DOI":"10.1049\/ip-ifs:20055006","volume":"152","author":"M. Feldhofer","year":"2005","unstructured":"Feldhofer, M., Wolkerstorfer, J., Rijmen, V.: AES implementation on a grain of sand. IEE Proc. Inf. Secur.\u00a0152(1), 13\u201320 (2005)","journal-title":"IEE Proc. Inf. Secur."},{"key":"45_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"319","DOI":"10.1007\/978-3-540-45238-6_26","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2003","author":"P. Chodowiec","year":"2003","unstructured":"Chodowiec, P., Gaj, K.: Very compact FPGA implementation of the AES algorithm. In: D.Walter, C., Ko\u00e7, \u00c7.K., Paar, C. (eds.) CHES 2003. LNCS, vol.\u00a02779, pp. 319\u2013333. Springer, Heidelberg (2003)"},{"key":"45_CR14","doi-asserted-by":"crossref","unstructured":"H\u00e4m\u00e4l\u00e4inen, P., H\u00e4nnik\u00e4inen, M., H\u00e4m\u00e4l\u00e4inen, T.: Efficient hardware implementation of security processing for IEEE 802.15.4 wireless networks. In: Proc. 48th IEEE Int. Midwest Symp. on Circuits and Systems (MWSCAS 2005), Cincinnati, OH, USA, August 7-10, 2005, pp. 484\u2013487 (2005)","DOI":"10.1109\/MWSCAS.2005.1594143"},{"key":"45_CR15","unstructured":"Rouvroy, G., Standaert, F.X., Quisquater, J.J., Legat, J.D.: Compact and efficient encryption\/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications. In: Proc. IEEE Int. Conf. on Inf. Tech.: Coding and Computing (ITCC 2004), Las Vegas, NV, USA, April 4-6, 2004, vol.\u00a02, pp. 583\u2013587 (2004)"},{"key":"45_CR16","unstructured":"Elbirt, A.J., Yip, W., Chetwynd, B., Paar, C.: An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists. In: Proc. 3rd AES Candidate Conf. (AES3), New York, NY, USA (April 13-14, 2000)"},{"key":"45_CR17","unstructured":"H\u00e4m\u00e4l\u00e4inen, P.: Cryptographic Security Designs and Hardware Architectures for Wireless Local Area Networks. PhD thesis, Tampere Univ. of Tech. Tampere, Finland, (December 2006), Available online: \n                    \n                      http:\/\/www.tkt.cs.tut.fi\/research\/daci\/phd_hamalainenp_thesis.html"},{"key":"45_CR18","unstructured":"Fischer, V.: Realization of the round 2 AES candidates using Altera FPGA. In: Proc. 3rd AES Candidate Conf. (AES3), New York, NY, USA (April 13-1, 4 2000)"},{"key":"45_CR19","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"77","DOI":"10.1007\/3-540-44709-1_8","volume-title":"Cryptographic Hardware and Embedded Systems - CHES 2001","author":"V. Fischer","year":"2001","unstructured":"Fischer, V., Drutarovsky, M.: Two methods of Rijndael implementation in reconfigurable hardware. In: Ko\u00e7, \u00c7.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol.\u00a02162, pp. 77\u201392. Springer, Heidelberg (2001)"},{"key":"45_CR20","doi-asserted-by":"crossref","unstructured":"H\u00e4m\u00e4l\u00e4inen, P., Alho, T., H\u00e4nnik\u00e4inen, M., H\u00e4m\u00e4l\u00e4inen, T.D.: Design and implementation of low-area and low-power AES encryption hardware core. In: Proc. 9th Euromicro Conf. Digital System Design (DSD 2006), Cavtat, Croatia (August 30-September 1, 2006), pp. 577\u2013583 (2006)","DOI":"10.1109\/DSD.2006.40"},{"key":"45_CR21","unstructured":"J\u00e4rvinen, T., Salmela, P., H\u00e4m\u00e4l\u00e4inen, P., Takala, J.: Efficient byte permutation realizations for compact AES implementations. In: Proc. 13th European Signal Processing Conf. (EUSIPCO 2005), Antalya, Turkey, September 4-8, 2005 (2005)"},{"key":"45_CR22","unstructured":"Ravi, S., Raghunathan, A., Potlapally, N., Sankaradass, M.: System design methodologies for a wireless security processing platform. In: Proc. 39th Design Automation Conf. New Orleans, LA, USA, June 10-14, 2002, pp. 777\u2013782 (2002)"},{"key":"45_CR23","doi-asserted-by":"crossref","unstructured":"Lewis, M., Simmons, S.: A VLSI implementation of a cryptographic processor. In: Proc. Canadian Conf. Electrical and Computer Engineering (CCECE 2003), Montreal, Canada, May 4-7, 2003, pp. 821\u2013826 (2003)","DOI":"10.1109\/CCECE.2003.1226021"},{"key":"45_CR24","doi-asserted-by":"crossref","unstructured":"H\u00e4m\u00e4l\u00e4inen, P., Heikkinen, J., H\u00e4nnik\u00e4inen, M., H\u00e4m\u00e4l\u00e4inen, T.D.: Design of transport triggered architecture processors for wireless encryption. In: Proc. 8th Euromicro Conf. Digital System Design (DSD 2005), Porto, Portugal, August 30-September 3, 2005, pp. 144\u2013152 (2005)","DOI":"10.1109\/DSD.2005.33"},{"issue":"1","key":"45_CR25","doi-asserted-by":"publisher","first-page":"43","DOI":"10.1109\/TVLSI.2005.863188","volume":"14","author":"Y. Eslami","year":"2006","unstructured":"Eslami, Y., Sheikholeslami, A., Gulak, P.G., Masui, S., Mukaida, K.: An area-efficient universal cryptography processor for smart cards. IEEE Trans. VLSI Systems\u00a014(1), 43\u201356 (2006)","journal-title":"IEEE Trans. VLSI Systems"},{"key":"45_CR26","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"11","DOI":"10.1007\/11552055_2","volume-title":"Communications and Multimedia Security","author":"S. Tillich","year":"2005","unstructured":"Tillich, S., Grossch\u00e4dl, J., Szekely, A.: An instruction set extension for fast and memory-efficient AES implementation. In: Dittmann, J., Katzenbeisser, S., Uhl, A. (eds.) CMS 2005. LNCS, vol.\u00a03677, pp. 11\u201321. Springer, Heidelberg (2005)"}],"container-title":["Lecture Notes in Computer Science","Embedded Computer Systems: Architectures, Modeling, and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-73625-7_45.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T09:54:33Z","timestamp":1619517273000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-73625-7_45"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540736226"],"references-count":26,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-73625-7_45","relation":{},"subject":[]}}