{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T06:13:22Z","timestamp":1775456002287,"version":"3.50.1"},"publisher-location":"Berlin, Heidelberg","reference-count":21,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"value":"9783540743088","type":"print"},{"value":"9783540743095","type":"electronic"}],"license":[{"start":{"date-parts":[[2007,1,1]],"date-time":"2007-01-01T00:00:00Z","timestamp":1167609600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1007\/978-3-540-74309-5_28","type":"book-chapter","created":{"date-parts":[[2007,8,20]],"date-time":"2007-08-20T06:34:15Z","timestamp":1187591655000},"page":"290-303","source":"Crossref","is-referenced-by-count":10,"title":["Synchronization Mechanisms on Modern Multi-core Architectures"],"prefix":"10.1007","author":[{"given":"Shaoshan","family":"Liu","sequence":"first","affiliation":[]},{"given":"Jean-Luc","family":"Gaudiot","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"28_CR1","doi-asserted-by":"crossref","unstructured":"Hammond, L., Wong, V., Chen, M., Carlstrom, B.D., Davis, J.D., Hertzberg, B., Prabhu, M.K., Wijaya, H., Kozyrakis, C., Olukotun, K.: Transactional memory coherence and consistency. In: ISCA 31, pp. 102\u2013113 (June 2004)","DOI":"10.1145\/1028176.1006711"},{"key":"28_CR2","doi-asserted-by":"crossref","unstructured":"Herlihy, M., Moss, J.E.B.: Transactional memory: Architectural support for lock-free data structures. In: ISCA\u00a020, 289\u2013300 (May 1993)","DOI":"10.1145\/173682.165164"},{"key":"28_CR3","volume-title":"Computer Architecture-A Quantitative Approach","author":"J.L. Hennessy","year":"2006","unstructured":"Hennessy, J.L., Patterson, D.A.: Computer Architecture-A Quantitative Approach. Morgan Kaufmann, San Francisco (2006)"},{"key":"28_CR4","unstructured":"Yamawaki, A., Iwane, M.: Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. In: Proc. of ISPAN 8 (2005)"},{"key":"28_CR5","doi-asserted-by":"crossref","unstructured":"Vadlamani, S., Jenks, S.: Architectural Considerations for Efficient Software Execution on Parallel Microprocessors. In: Proc. of IPDPS 21 (2007)","DOI":"10.1109\/IPDPS.2007.370294"},{"key":"28_CR6","doi-asserted-by":"crossref","unstructured":"Monchiero, M., Palermo, G., Silvano, C., Villa, O.: An Efficient Synchronization Technique for Multiprocessor Systems on-Chip. ACM SIGARCH Computer Architecture News\u00a034(1) (March 2006)","DOI":"10.1145\/1147349.1147357"},{"key":"28_CR7","doi-asserted-by":"crossref","unstructured":"Zhu, W., Sreedhar, V.C., Hu, Z., Gao, G.R.: Synchronization State Buffer: Supporting Efficient Fine-Grain Synchronization on Many-Core Architectures. In: ISCA, 34 (June 2007)","DOI":"10.1145\/1250662.1250668"},{"key":"28_CR8","doi-asserted-by":"crossref","unstructured":"Kongetira, P., Aingaran, K., Olukotun, K.: A 32-way multithreaded Sparc processor. IEEE Micro., 40\u201347 (March\/April 2005)","DOI":"10.1109\/MM.2005.35"},{"key":"28_CR9","unstructured":"Denneau, M., Warren Jr., H.S.: 64-bit Cyclops: Principles of operation (April 2005)"},{"key":"28_CR10","doi-asserted-by":"crossref","unstructured":"Vangal, S., Howard, J., Ruhl, G., et al.: An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS. In: Procs. of ISSCC 2007 (February 2007)","DOI":"10.1109\/ISSCC.2007.373606"},{"key":"28_CR11","unstructured":"Held, J., Bautista, J., Koehl, S.: From a Few Cores to Many: A Tera-Scale Computing Research Review, White Paper, Intel Research2006 (2006)"},{"key":"28_CR12","unstructured":"Asanovic, K., Bodik, R., Catanzaro, B.C., Gebis, J.J, Husbands, P., Keutzer, K., Patterson, D.A., Plishker, W.L., Shalf, J., Williams, S.W., Yelick, K.A.: The Landscape of Parallel Computing Research: A View from Berkeley. Technical Report No. UCB\/EECS-2006-183 (December 2006)"},{"key":"28_CR13","doi-asserted-by":"crossref","unstructured":"Kumar, R., Tullsen, D.M., Jouppi, N.P.: Heterogeneous Chip Multiprocessors. Computer, IEEE Computer Society (2005)","DOI":"10.1109\/MC.2005.379"},{"key":"28_CR14","doi-asserted-by":"crossref","unstructured":"Jasionowski, B. J.,Lay, M. K., Margala, M.: A Processor-In-Memory Architecture for Multimedia Compression. IEEE Transaction on VLSI Systems (April 2007)","DOI":"10.1109\/TVLSI.2007.893672"},{"key":"28_CR15","doi-asserted-by":"crossref","unstructured":"Sterling, T.L., Zima, H.P.: Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing. ACM\/IEEE Supercomputing Conference (2002)","DOI":"10.1109\/SC.2002.10061"},{"key":"28_CR16","doi-asserted-by":"crossref","unstructured":"Breach, S.E., Vijaykumar, T.N., Sohi, G.S.: The Anatomy of the Register File in a Multiscalar Processor. In: Proc. MICRO-27 (December 1994)","DOI":"10.1145\/192724.192750"},{"key":"28_CR17","doi-asserted-by":"crossref","unstructured":"Keckler, S.W., Dally, W.J., Maskit, D., Carter, N.P., Chang, A., Lee, W.S.: Exploiting Fine-Grain Thread Level Parallelism on the MIT Multi-ALU Processor. In: Proc. 25th ISCA (June 1998)","DOI":"10.1145\/279361.279399"},{"key":"28_CR18","doi-asserted-by":"crossref","unstructured":"Kobayashi, R., Iwata, M., Ogawa, Y., Ando, H., Shimada, T.: An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. In: Proc. 25th EUROMICRO (1999)","DOI":"10.1109\/EURMIC.1999.794505"},{"key":"28_CR19","unstructured":"Lin, W.-Y., Gaudiot, J.-L., Amaral, J.N., Gao, G.R.: Performance Analysis of the I-Structure Software Cache on Multi-Threading Systems. In: IPCCC 2000. Proc. of the 19th IEEE International Performance, Computing, and Communication Conference (February 2000)"},{"key":"28_CR20","unstructured":"Lin, W.-Y., Amaral, J.N., Gaudiot, J.-L., Gao, G.R.: Caching Single-Assignment Structures to Build a Robust Fine-Grain Multi-Threading System. In: IPDPS 2000. Proc. of the 14th International Parallel and Distributed Processing Symposium (May 2000)"},{"issue":"4","key":"28_CR21","doi-asserted-by":"publisher","first-page":"598","DOI":"10.1145\/69558.69562","volume":"11","author":"N.R.S. Arvind","year":"1989","unstructured":"Arvind, N.R.S., Pingali, K.K.: I-structures: data structures for parallel computing. ACM Transactions on Programming Languages and Systems (TOPLAS)\u00a011(4), 598\u2013632 (1989)","journal-title":"ACM Transactions on Programming Languages and Systems (TOPLAS)"}],"container-title":["Lecture Notes in Computer Science","Advances in Computer Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-74309-5_28","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,21]],"date-time":"2019-05-21T21:10:19Z","timestamp":1558473019000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-74309-5_28"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"ISBN":["9783540743088","9783540743095"],"references-count":21,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-74309-5_28","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"value":"0302-9743","type":"print"},{"value":"1611-3349","type":"electronic"}],"subject":[],"published":{"date-parts":[[2007]]}}}