{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T01:50:53Z","timestamp":1725501053708},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540744412"},{"type":"electronic","value":"9783540744429"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-74442-9_18","type":"book-chapter","created":{"date-parts":[[2007,8,20]],"date-time":"2007-08-20T08:15:44Z","timestamp":1187597744000},"page":"181-190","source":"Crossref","is-referenced-by-count":3,"title":["Logic Style Comparison for Ultra Low Power Operation in 65nm Technology"],"prefix":"10.1007","author":[{"given":"Mandeep","family":"Singh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christophe","family":"Giacomotto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bart","family":"Zeydel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vojin","family":"Oklobdzija","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"18_CR1","doi-asserted-by":"crossref","first-page":"991","DOI":"10.1016\/S0026-2692(00)00088-4","volume":"31","author":"D. Marcovic","year":"2000","unstructured":"Marcovic, D., Nikolic, B., Oklobdzija, V.G.: A general method in synthesis of pass-transistor circuits. Elsevier Microelectronics Journal\u00a031, 991\u2013998 (2000)","journal-title":"Elsevier Microelectronics Journal"},{"issue":"7","key":"18_CR2","first-page":"1079","volume":"32","author":"R. Zimmermann","year":"1997","unstructured":"Zimmermann, R., Fichtner, W.: Low-power logic styles: CMOS versus pass-transistor logic, Solid-State Circuits. IEEE Journal\u00a032(7), 1079\u20131090 (1997)","journal-title":"IEEE Journal"},{"key":"18_CR3","doi-asserted-by":"crossref","unstructured":"Shams, A.M., Darwish, T.K.: Performance Analysis of 1-Bit CMOS Full Adder Cells. IEEE Trans. On Very Large Scale Integration (VLSI) Systems\u00a010(1) (2002)","DOI":"10.1109\/92.988727"},{"key":"18_CR4","doi-asserted-by":"crossref","unstructured":"Shalem, R., John, E., John, L.K.: A novel low power energy recovery full adder cell. In: VLSI 1999 Proceedings. Ninth Great Lakes Symposium (4-6 March, 1999)","DOI":"10.1109\/GLSV.1999.757461"},{"key":"18_CR5","doi-asserted-by":"crossref","unstructured":"Radhakrishnan, D.: Low Voltage, low power CMOS full adder. IEE Proc-Circuits Devices Syst.\u00a0148(1) (February 2001)","DOI":"10.1049\/ip-cds:20010170"},{"key":"18_CR6","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"148","DOI":"10.1007\/11847083_15","volume-title":"Integrated Circuit and System Design","author":"M. Vratonjic","year":"2006","unstructured":"Vratonjic, M., Zeydel, B.R., Oklobdzija, V.G.: Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design. In: Vounckx, J., Azemard, N., Maurine, P. (eds.) PATMOS 2006. LNCS, vol.\u00a04148, pp. 148\u2013156. Springer, Heidelberg (2006)"},{"issue":"2","key":"18_CR7","doi-asserted-by":"publisher","first-page":"122","DOI":"10.1109\/TVLSI.2005.863760","volume":"14","author":"H.Q. Dao","year":"2006","unstructured":"Dao, H.Q., Zeydel, B.R., Oklobdzija, V.G.: Energy Optimization of Pipelined Digital Systems Using Circuit Sizing and Supply Scaling. IEEE Transaction on VLSI Systems\u00a014(2), 122\u2013134 (2006)","journal-title":"IEEE Transaction on VLSI Systems"},{"key":"18_CR8","unstructured":"Kao, J., Chandraksan, A.: MTCMOS Sequential Circuits. ESSCIRC (September 2001)"},{"key":"18_CR9","unstructured":"Song, M., Asada, K.: Desing of Low Power Digital VLSI Circuits Based on Novel Pass transistor logic. IEICE Trans. Electron.\u00a0E81-C(11) (November 1998)"},{"key":"18_CR10","doi-asserted-by":"crossref","unstructured":"Lindert, N., Sugii, T.: Dynamic Threshold Pass Transistor Logic for Improved delay at Low power supply voltages. IEEE JSSC\u00a034(1) (January 1999)","DOI":"10.1109\/4.736659"},{"key":"18_CR11","doi-asserted-by":"crossref","unstructured":"Calhoun, B.H., Honor\u00e9, F.A, Chandrakasan, A.P.: A Leakage reduction methodology for Distributed MTCMOS. IEEE JSSC\u00a039(5) (May 2004)","DOI":"10.1109\/JSSC.2004.826335"},{"key":"18_CR12","doi-asserted-by":"crossref","unstructured":"Bui, H.T., Wang, Y., Jiang, Y.: Design and Analysis of Low Power 10 Transistor Full Adders Using Novel XOR XNOR gates. IEEE Transactions on Circuits and Systems \u2013 II\u00a049(1) (January 2002)","DOI":"10.1109\/82.996055"},{"key":"18_CR13","unstructured":"Wang, A., Chandrakasan, A.: A 180mV FFT Processor Using Subthreshold Circuit Techniques. In: Proceeds, IEEE International Solid State Circuits Conference (2004)"},{"key":"18_CR14","doi-asserted-by":"crossref","unstructured":"Calhoun, B.H., Wang, A., Chandrakasan, A.P.: Device Sizing for Minimum Energy Operation in Subthreshold Circuits. In: IEEE Custom Integrated Circuits Conference (CICC), October 2004, pp. 95\u201398 (2004)","DOI":"10.1109\/CICC.2004.1358745"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-74442-9_18.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T10:26:42Z","timestamp":1619519202000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-74442-9_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540744412","9783540744429"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-74442-9_18","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[]}}