{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T14:10:48Z","timestamp":1737382248006,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540744412"},{"type":"electronic","value":"9783540744429"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-74442-9_3","type":"book-chapter","created":{"date-parts":[[2007,8,20]],"date-time":"2007-08-20T08:15:44Z","timestamp":1187597744000},"page":"20-30","source":"Crossref","is-referenced-by-count":2,"title":["A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms"],"prefix":"10.1007","author":[{"given":"Ioannis","family":"Panagopoulos","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Christos","family":"Pavlatos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George","family":"Manis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George","family":"Papakonstantinou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"3_CR1","volume-title":"Surviving the SOC Revolution","author":"H. Chang","year":"1999","unstructured":"Chang, H., Cooke, L., Hunt, M., Marting, G., McNelly, A., Todd, L.: Surviving the SOC Revolution. Kluwer Academic Publishers, Dordrecht (1999)"},{"key":"3_CR2","doi-asserted-by":"crossref","unstructured":"Li, Y., Callahan, T., Darnell, E., Harr, R., Kurkure, U., Stockwood, J.: Hardware-Software Co-Design of Embedded Reconfigurable Architectures. In: DAC 2000, pp. 507\u2013512 (2000)","DOI":"10.1145\/337292.337559"},{"key":"3_CR3","doi-asserted-by":"crossref","unstructured":"Economacos, G., Economacos, P., Poulakis, I., Panagopoulos, I., Papakonstantinou, G.: Behavioural synthesis with Systemc. In: Design Automation and Test in Europe Conference and Exhibition (DATE 2001), Munich, Germany, pp. 21\u201325 (2001)","DOI":"10.1109\/DATE.2001.914995"},{"key":"3_CR4","doi-asserted-by":"publisher","first-page":"185","DOI":"10.1007\/s11227-006-2953-0","volume":"35","author":"M.D. Galanis","year":"2006","unstructured":"Galanis, M.D., Dimitroulakos, G., Goutis, C.: Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs. The Journal of SuperComputing\u00a035, 185\u2013199 (2006)","journal-title":"The Journal of SuperComputing"},{"key":"3_CR5","volume-title":"Parallel Processing: From Applications to Systems","author":"D. Moldovan","year":"1993","unstructured":"Moldovan, D.: Parallel Processing: From Applications to Systems. Morgan Kaufmann, San Mateo, CA (1993U)"},{"issue":"7","key":"3_CR6","doi-asserted-by":"publisher","first-page":"366","DOI":"10.1109\/TCSII.2005.850432","volume":"52","author":"C. Cheng","year":"2005","unstructured":"Cheng, C., Parhi, K.K.: A Novel Systolic Array Structure for DCT. IEEE Transactions on Circuits and Systems\u00a052(7), 366\u2013369 (2005)","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"3_CR7","doi-asserted-by":"publisher","first-page":"149","DOI":"10.1023\/A:1024447517501","volume":"26","author":"M. Bednara","year":"2003","unstructured":"Bednara, M., Teich, J.: Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. The Journal of Supercomputing\u00a026, 149\u2013165 (2003)","journal-title":"The Journal of Supercomputing"},{"issue":"10","key":"3_CR8","doi-asserted-by":"publisher","first-page":"1001","DOI":"10.1109\/TSE.1985.231547","volume":"11","author":"C.P. Kruskal","year":"1985","unstructured":"Kruskal, C.P., Weiss, A.: Allocating independent subtasks on parallel processors. IEEE Trans. On Software Engineering\u00a011(10), 1001\u20131016 (1985)","journal-title":"IEEE Trans. On Software Engineering"},{"key":"3_CR9","doi-asserted-by":"crossref","unstructured":"Ciorba, F.M., Andronikos, T., Riakiotakis, I., Chronopoulos, A.T., Papakonstantinou, G.: Dynamic Multi Phase Scheduling for Heterogeneous Clusters. In: Proc. of the 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2006), Rhodes, Greece (2006)","DOI":"10.1109\/IPDPS.2006.1639308"},{"key":"3_CR10","doi-asserted-by":"crossref","unstructured":"Andronikos, T., Koziris, N., Papakonstantinou, G., Tsanakas, P.: Optimal Scheduling for UET-UCT Generalized n-Dimensional Grid Task Graphs. In: Proceedings of the 11 th IEEE\/ACM International Parallel Processing Symposium (IPPS 1997), Geneva, Switzerland, p. 146151 (1997)","DOI":"10.1109\/IPPS.1997.580872"},{"key":"3_CR11","unstructured":"Panagopoulos, I., Pavlatos, C., Dimopoulos, A., Papakonstantinou, G.: Hardware Solution of a First-Order Diophantine Equation. In: HERCMA 2007, Athens, Greece (to be presented)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-74442-9_3.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T13:34:14Z","timestamp":1737380054000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-74442-9_3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540744412","9783540744429"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-74442-9_3","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[]}}