{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T01:50:54Z","timestamp":1725501054459},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540744412"},{"type":"electronic","value":"9783540744429"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-74442-9_46","type":"book-chapter","created":{"date-parts":[[2007,8,20]],"date-time":"2007-08-20T08:15:44Z","timestamp":1187597744000},"page":"474-484","source":"Crossref","is-referenced-by-count":1,"title":["Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates"],"prefix":"10.1007","author":[{"given":"Paulo F.","family":"Butzen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andr\u00e9 I.","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris H.","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Renato P.","family":"Ribas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"issue":"2","key":"46_CR1","doi-asserted-by":"publisher","first-page":"302","DOI":"10.1109\/JPROC.2002.808156","volume":"91","author":"K. Roy","year":"2003","unstructured":"Roy, K., Mukhopadhyay, S., Meimand, H.M.: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proceedings of the IEEE\u00a091(2), 302\u2013327 (2003)","journal-title":"Proceedings of the IEEE"},{"issue":"3","key":"46_CR2","doi-asserted-by":"crossref","first-page":"423","DOI":"10.1109\/TCAD.2005.853692","volume":"25","author":"J.H. Anderson","year":"2006","unstructured":"Anderson, J.H., Najm, F.N.: Active Leakage Power Optimization for FPGAs. IEEE Trans. on CAD\u00a025(3), 423\u2013437 (2006)","journal-title":"IEEE Trans. on CAD"},{"unstructured":"Yang, S., Wolf, W., Vijaykrishnan, N., Xie, Y., Wang, W.: Accurate Stacking Effect Macro-modeling of Leakage Power in Sub-100nm Circuits. In: Proc. Int. Conference on VLSI Design, January 2005, pp. 165\u2013170 (2005)","key":"46_CR3"},{"doi-asserted-by":"crossref","unstructured":"Gu, R.X., Elmasry, M.I.: Power Distribution Analysis and Optimization of Deep Submicron CMOS Digital Circuit. IEEE J. Solid-State Circuits\u00a031 (May 1996)","key":"46_CR4","DOI":"10.1109\/4.509853"},{"doi-asserted-by":"crossref","unstructured":"Cheng, Z., Johnson, M., Wei, L., Roy, K.: Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks. In: Proc. Int. Symposium Low Power Electronics and Design, August 1998, pp. 239\u2013244 (1998)","key":"46_CR5","DOI":"10.1145\/280756.280917"},{"key":"46_CR6","volume-title":"Low-Power CMOS VLSI Circuit Design","author":"K. Roy","year":"2000","unstructured":"Roy, K., Prasad, S.: Low-Power CMOS VLSI Circuit Design. John Wiley & Sons, Chichester (2000)"},{"key":"46_CR7","volume-title":"Leakage in Nanometer CMOS Technologies","author":"S.G. Narendra","year":"2006","unstructured":"Narendra, S.G., Chandrakasan, A.: Leakage in Nanometer CMOS Technologies. Springer, Heidelberg (2006)"},{"key":"46_CR8","series-title":"Lecture Notes in Computer Science","volume-title":"Integrated Circuit and System Design","author":"J.L. Rossel\u00f3","year":"2006","unstructured":"Rossel\u00f3, J.L., Bota, S., Segura, J.: Compact Static Power Model of Complex CMOS Gates. In: Vounckx, J., Azemard, N., Maurine, P. (eds.) PATMOS 2006. LNCS, vol.\u00a04148, Springer, Heidelberg (2006)"},{"doi-asserted-by":"crossref","unstructured":"Lee, D., Kwong, W., Blaauw, D., Sylvester, D.: Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage. In: Proc. DAC, June 2003, pp. 175\u2013180 (2003)","key":"46_CR9","DOI":"10.1145\/775832.775878"},{"doi-asserted-by":"crossref","unstructured":"Gavrilov, S., et al.: Library-less Synthesis for Static CMOS Combinational Logic Circuits. In: Proc. ICCAD, November 1997, pp. 658\u2013662 (1997)","key":"46_CR10","DOI":"10.1109\/ICCAD.1997.643608"},{"issue":"7","key":"46_CR11","doi-asserted-by":"crossref","first-page":"866","DOI":"10.1109\/TCAD.2002.1013899","volume":"21","author":"C. Yang","year":"2002","unstructured":"Yang, C., Ciesielski, M.: BDS: a BDD-based logic optimization system. IEEE Trans. CAD\u00a021(7), 866\u2013876 (2002)","journal-title":"IEEE Trans. CAD"},{"unstructured":"Lindgren, P., Kerttu, M., Thornton, M., Drechsler, R.: Low power optimization technique for BDD mapped circuits. In: ASP-DAC 2001, 615\u2013621 (2001)","key":"46_CR12"},{"issue":"8","key":"46_CR13","doi-asserted-by":"publisher","first-page":"957","DOI":"10.1109\/TVLSI.2005.853601","volume":"13","author":"R.S. Shelar","year":"2005","unstructured":"Shelar, R.S., Sapatnekar, S.: BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. VLSI\u00a013(8), 957\u2013970 (2005)","journal-title":"IEEE Trans. VLSI"},{"doi-asserted-by":"crossref","unstructured":"Sheu, B.J., Scharfetter, D.L., Ko, P.K., Jeng, M.C.: BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors. IEEE J. Solid-State Circuits\u00a0SC-22 (August 1987)","key":"46_CR14","DOI":"10.1109\/JSSC.1987.1052773"},{"doi-asserted-by":"crossref","unstructured":"Butzen, P.F., Reis, A.I., Kim, C.H., Ribas, R.P.: Modeling Subthreshold Leakage Current in General Transistor Networks. In: Proc. ISVLSI (May 2007)","key":"46_CR15","DOI":"10.1109\/ISVLSI.2007.68"},{"key":"46_CR16","volume-title":"Logical Effort: Designing Fast CMOS Circuits","author":"I. Sutherland","year":"1999","unstructured":"Sutherland, I., Sproull, B., Harris, D.: Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, San Francisco, CA (1999)"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-74442-9_46.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T10:27:04Z","timestamp":1619519224000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-74442-9_46"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540744412","9783540744429"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-74442-9_46","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[]}}