{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T16:16:27Z","timestamp":1742400987661},"publisher-location":"Berlin, Heidelberg","reference-count":10,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540744412"},{"type":"electronic","value":"9783540744429"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-74442-9_53","type":"book-chapter","created":{"date-parts":[[2007,8,20]],"date-time":"2007-08-20T04:15:44Z","timestamp":1187583344000},"page":"546-555","source":"Crossref","is-referenced-by-count":11,"title":["Low-Power Digital Filtering Based on the Logarithmic Number System"],"prefix":"10.1007","author":[{"given":"Ch.","family":"Basetas","sequence":"first","affiliation":[]},{"given":"I.","family":"Kouretas","sequence":"additional","affiliation":[]},{"given":"V.","family":"Paliouras","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"53_CR1","doi-asserted-by":"publisher","first-page":"23","DOI":"10.1109\/101.950050","volume":"17","author":"T. Stouraitis","year":"2001","unstructured":"Stouraitis, T., Paliouras, V.: Considering the alternatives in low-power design. IEEE Circuits and Devices\u00a017, 23\u201329 (2001)","journal-title":"IEEE Circuits and Devices"},{"key":"53_CR2","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1109\/92.386219","volume":"3","author":"P.E. Landman","year":"1995","unstructured":"Landman, P.E., Rabaey, J.M.: Architectural power analysis: The dual bit type method. IEEE Transactions on VLSI Systems\u00a03, 173\u2013187 (1995)","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"53_CR3","doi-asserted-by":"publisher","first-page":"1040","DOI":"10.1109\/12.156547","volume":"41","author":"M.G. Arnold","year":"1992","unstructured":"Arnold, M.G., Bailey, T.A., Cowles, J.R., Winkel, M.D.: Applying features of the IEEE 754 to sign\/logarithm arithmetic. IEEE Transactions on Computers\u00a041, 1040\u20131050 (1992)","journal-title":"IEEE Transactions on Computers"},{"key":"53_CR4","first-page":"2512","volume-title":"Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing","author":"J..R.E. Morley","year":"1988","unstructured":"Morley, J. R.E., Engel, G.L., Sullivan, T.J., Natarajan, S.M.: VLSI based design of a battery-operated digital hearing aid. In: Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, 1988, pp. 2512\u20132515. IEEE Computer Society Press, Los Alamitos (1988)"},{"key":"53_CR5","doi-asserted-by":"crossref","unstructured":"Sacha, J.R., Irwin, M.J.: Number representation for reducing switched capacitance in subband coding. In: Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 1998, pp. 3125\u20133128 (1998)","DOI":"10.1109\/ICASSP.1998.678188"},{"key":"53_CR6","volume-title":"Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, (ASAP 2002)","author":"M.G. Arnold","year":"2002","unstructured":"Arnold, M.G.: Reduced power consumption for mpeg decoding with lns. In: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2002), IEEE Computer Society Press, Los Alamitos (2002)"},{"key":"53_CR7","doi-asserted-by":"crossref","unstructured":"Kang, B., Vijaykrishnan, N., Irwin, M.J., Theocharides, T.: Power-efficient implementation of turbo decoder in sdr system. In: Proceedings of the IEEE International SOC Conference, pp. 119\u2013122 (2004)","DOI":"10.1109\/SOCC.2004.1362372"},{"key":"53_CR8","doi-asserted-by":"crossref","unstructured":"Paliouras, V., Stouraitis, T.: Low-power properties of the Logarithmic Number System. In: Proceedings of 15th Symposium on Computer Arithmetic (ARITH15), Vail, CO, June 2001, pp. 229\u2013236 (2001)","DOI":"10.1109\/ARITH.2001.930124"},{"key":"53_CR9","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"285","DOI":"10.1007\/3-540-45373-3_30","volume-title":"Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation","author":"V. Paliouras","year":"2000","unstructured":"Paliouras, V., Stouraitis, T.: Logarithmic number system for low-power arithmetic. In: Soudris, D.J., Pirsch, P., Barke, E. (eds.) PATMOS 2000. LNCS, vol.\u00a01918, pp. 285\u2013294. Springer, Heidelberg (2000)"},{"key":"53_CR10","doi-asserted-by":"publisher","first-page":"190","DOI":"10.1109\/12.2148","volume":"37","author":"F. Taylor","year":"1988","unstructured":"Taylor, F., Gill, R., Joseph, J., Radke, J.: A 20 bit Logarithmic Number System processor. IEEE Transactions on Computers\u00a037, 190\u2013199 (1988)","journal-title":"IEEE Transactions on Computers"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-74442-9_53.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T06:27:16Z","timestamp":1619504836000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-74442-9_53"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540744412","9783540744429"],"references-count":10,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-74442-9_53","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[]}}