{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T01:50:54Z","timestamp":1725501054465},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540744412"},{"type":"electronic","value":"9783540744429"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-74442-9_7","type":"book-chapter","created":{"date-parts":[[2007,8,20]],"date-time":"2007-08-20T04:15:44Z","timestamp":1187583344000},"page":"64-74","source":"Crossref","is-referenced-by-count":0,"title":["A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs"],"prefix":"10.1007","author":[{"given":"Noureddine","family":"Chabini","sequence":"first","affiliation":[]}],"member":"297","reference":[{"issue":"1","key":"7_CR1","doi-asserted-by":"publisher","first-page":"6","DOI":"10.1109\/7384.928306","volume":"1","author":"L. Benini","year":"2001","unstructured":"Benini, L., Macii, E., De Micheli, G.: Designing Low Power Circuits: Practical Recipes. IEEE Circuit and System Magazine\u00a01(1), 6\u201325 (2001)","journal-title":"IEEE Circuit and System Magazine"},{"key":"7_CR2","volume-title":"High-Level Power Analysis and Optimization","author":"A. Raghunathan","year":"1997","unstructured":"Raghunathan, A., et al.: High-Level Power Analysis and Optimization. Kluwer, Norwell, MA (1997)"},{"key":"7_CR3","doi-asserted-by":"crossref","unstructured":"Usami, K., Horowitz, M.: Clustered voltage scaling technique for low-power design. In: Proceedings of Int. Workshop on Low Power Design, pp. 3\u20138 (1995)","DOI":"10.1145\/224081.224083"},{"issue":"3","key":"7_CR4","doi-asserted-by":"publisher","first-page":"463","DOI":"10.1109\/4.661212","volume":"33","author":"K. Usami","year":"1998","unstructured":"Usami, K., et al.: Automated low power technique exploiting multiple supply voltages applied to a media processor. IEEE Journal of Solid-State Circuits\u00a033(3), 463\u2013472 (1998)","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"7_CR5","doi-asserted-by":"crossref","unstructured":"Pering, T., Burd, T.D., Brodersen, R.W.: Voltage scheduling in the IpARM microprocessor system. In: Proceedings of Int. Symp. on Low Power Electron, Design, pp. 96\u2013101 (2000)","DOI":"10.1145\/344166.344530"},{"key":"7_CR6","doi-asserted-by":"crossref","unstructured":"Chabini, N., Chabini, I., Aboulhamid, E.-M., Savaria, Y.: Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. In: Proc. Great Lakes Symp. on VLSI, Washington, DC, pp. 221\u2013224 (2003)","DOI":"10.1145\/764808.764865"},{"issue":"4","key":"7_CR7","doi-asserted-by":"publisher","first-page":"436","DOI":"10.1109\/92.645070","volume":"5","author":"J. Chang","year":"1997","unstructured":"Chang, J., Pedram, M.: Energy Minimization Using Multiple Supply Voltages. IEEE Transactions on Very Large Scale Integration Systems\u00a05(4), 436\u2013443 (1997)","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"key":"7_CR8","doi-asserted-by":"crossref","unstructured":"Leiserson, C.E, Saxe, J.B.: Retiming Synchronous Circuitry. Algorithmica, 5\u201335 (1991)","DOI":"10.1007\/BF01759032"},{"key":"7_CR9","doi-asserted-by":"publisher","first-page":"43","DOI":"10.1145\/589411.589422","volume-title":"Proceedings of the 8th ACM\/IEEE Workshop on Timing issues in the specification and synthesis of digital systems","author":"F. Sheikh","year":"2002","unstructured":"Sheikh, F., Kuehlmann, A., Keutzer, K.: Minimum-power retiming for dual-supply CMOS circuits. In: Proceedings of the 8th ACM\/IEEE Workshop on Timing issues in the specification and synthesis of digital systems, pp. 43\u201349. IEEE Computer Society Press, Los Alamitos (2002)"},{"key":"7_CR10","volume-title":"Introduction to Algorithms","author":"T.H. Cormen","year":"1990","unstructured":"Cormen, T.H., Leiserson, C.E., Rivest, R.L.: Introduction to Algorithms. McGraw-Hill, New York (1990)"},{"key":"7_CR11","volume-title":"Synthesis and Optimization of Digital Circuits","author":"G. Micheli De","year":"1994","unstructured":"De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, Inc., New York (1994)"},{"issue":"4","key":"7_CR12","doi-asserted-by":"publisher","first-page":"516","DOI":"10.1145\/502175.502180","volume":"6","author":"F.-R. Boyer","year":"2001","unstructured":"Boyer, F.-R., Aboulhamid, E.-M., Savaria, Y., Boyer, M.: Optimal design of synchronous circuits using software pipelining techniques. ACM Trans. Design Autom. Electr. Syst.\u00a06(4), 516\u2013532 (2001)","journal-title":"ACM Trans. Design Autom. Electr. Syst."}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-74442-9_7.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T06:27:26Z","timestamp":1619504846000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-74442-9_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540744412","9783540744429"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-74442-9_7","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[]}}