{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T22:55:24Z","timestamp":1725490524631},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540744825"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-74484-9_14","type":"book-chapter","created":{"date-parts":[[2007,8,28]],"date-time":"2007-08-28T21:48:03Z","timestamp":1188337683000},"page":"154-168","source":"Crossref","is-referenced-by-count":0,"title":["CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse"],"prefix":"10.1007","author":[{"given":"Lilian","family":"Janin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Doug","family":"Edwards","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"14_CR1","doi-asserted-by":"crossref","unstructured":"Moore, S., Taylor, G., Robinson, P., Mullins, R.: Point to Point GALS Interconnect. In: Eighth International Symposium on Asynchronus Circuits and Systems (ASYNC\u201902) (2002)","DOI":"10.1109\/ASYNC.2002.1000297"},{"issue":"5","key":"14_CR2","first-page":"16","volume":"22","author":"W.J. Bainbridge","year":"2002","unstructured":"Bainbridge, W.J., Furber, S.B.: CHAIN: A Delay Insensitive CHip Area INterconnect. IEEE Micro special issue on Design and Test of System on Chip\u00a022(5), 16\u201323 (2002)","journal-title":"IEEE Micro special issue on Design and Test of System on Chip"},{"key":"14_CR3","unstructured":"Parker, D.: Transactor generation using the CY language. SpiraTech Limited"},{"key":"14_CR4","unstructured":"TransactorWizard, http:\/\/www.sdvinc.com"},{"key":"14_CR5","doi-asserted-by":"crossref","unstructured":"Balarin, F., Passerone, R.: Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation. Design, Automation and Test in Europe (2006)","DOI":"10.1109\/DATE.2006.243899"},{"key":"14_CR6","unstructured":"Property Specification Language: Reference Manual, http:\/\/www.accellera.org\/pslv101.pdf"},{"key":"14_CR7","doi-asserted-by":"crossref","unstructured":"Hoare, C.A.R.: Communicating sequential processes. Comms. of the ACM\u00a021(8) (1978)","DOI":"10.1145\/359576.359585"},{"key":"14_CR8","unstructured":"Renaudin, M., Rigaud, J.B., et al.: TAST CAD Tools. ASYNC\u201902 Tutorial (2002)"},{"key":"14_CR9","doi-asserted-by":"crossref","unstructured":"Edwards, D., Bardsley, A.: Balsa: An Asynchronous Hardware Synthesis Language. The Computer Journal\u00a045(1), 12\u201318","DOI":"10.1093\/comjnl\/45.1.12"},{"key":"14_CR10","unstructured":"Balsamics, http:\/\/www.cs.manchester.ac.uk\/apt\/projects\/tools\/balsamics\/transactors"},{"key":"14_CR11","unstructured":"Open Core Protocol International Partnership, http:\/\/www.ocpip.org"}],"container-title":["Lecture Notes in Computer Science","Computational Science and Its Applications \u2013 ICCSA 2007"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-74484-9_14.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,11,19]],"date-time":"2020-11-19T05:22:37Z","timestamp":1605763357000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-74484-9_14"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540744825"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-74484-9_14","relation":{},"subject":[]}}