{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:58:07Z","timestamp":1725494287115},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540755951"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-75596-8_11","type":"book-chapter","created":{"date-parts":[[2007,11,3]],"date-time":"2007-11-03T10:03:37Z","timestamp":1194084217000},"page":"129-144","source":"Crossref","is-referenced-by-count":9,"title":["Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions"],"prefix":"10.1007","author":[{"given":"Bijan","family":"Alizadeh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masahiro","family":"Fujita","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"11_CR1","unstructured":"Alizadeh, B., Fujita, M.: LTED: A Canonical and Compact Hybrid Word-Boolean Representation as a Formal Model for Hardware\/Software Co-designs. In: CFV 2007. The fourth Workshop on Constraints in Formal Verification, pp. 15\u201329 (2007)"},{"key":"11_CR2","doi-asserted-by":"crossref","unstructured":"Vasudevan, S., Viswanath, V., Abraham, J., Tu, J.: Automatic Decomposition for Sequential Equivalence Checking of System Level and RTL Descriptions. In: MemoCode 2006. Proceedings of Formal Methods and Models for Co-Design, pp. 71\u201380 (2006)","DOI":"10.1109\/MEMCOD.2006.1695903"},{"key":"11_CR3","doi-asserted-by":"crossref","unstructured":"Feng, X., Hu, A.: Early Cutpoint Insertion for High-Level Software vs. RTL Formal Combinational Equivalence Verification. In: DAC 2006. Proceedings of 43th Design Automation Conference, pp. 1063\u20131068 (2006)","DOI":"10.1145\/1146909.1147178"},{"key":"11_CR4","doi-asserted-by":"crossref","unstructured":"Matsumoto, T., Saito, H., Fujita, M.: Equivalence checking of C programs by locally performing symbolic simulation on dependence graphs. In: ISQED 2006. Proceedings of 7th International Symposium on Quality Electronic Design, pp. 370\u2013375 (2006)","DOI":"10.1109\/ISQED.2006.61"},{"key":"11_CR5","doi-asserted-by":"crossref","unstructured":"Koelbl, A., Lu, Y., Mathur, A.: Embedded tutorial: Formal Equivalence Checking Between System-level Models and RTL. In: Proceedings of ICCAD 2005, pp. 965\u2013971 (2005)","DOI":"10.1109\/ICCAD.2005.1560201"},{"key":"11_CR6","doi-asserted-by":"crossref","unstructured":"Kroening, D., Clarke, E., Yorav, K.: Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking. In: DAC 2003. Proceedings of 40th Design Automation Conference, pp. 368\u2013371 (2003)","DOI":"10.1145\/775832.775928"},{"key":"11_CR7","doi-asserted-by":"crossref","unstructured":"Karfa, C., Mandal, C., Sarkar, D., Pentakota, S.R., Reade, C.: A Formal Verification Method of Scheduling in High-level Synthesis. In: ISQED 2006. Proceedings of 7th International Symposium on Quality Electronic Design, pp. 71\u201378 (2006)","DOI":"10.1109\/ISQED.2006.10"},{"key":"11_CR8","doi-asserted-by":"crossref","unstructured":"Fallah, F., Devadas, S., Keutzer, K.: Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. In: DAC 1998. Proceedings of 35th Design Automation Conference, pp. 528\u2013533 (1998)","DOI":"10.1145\/277044.277187"},{"key":"11_CR9","unstructured":"Alizadeh, B., Fujita, M.: A Hybrid Approach for Equivalence Checking Between System Level and RTL Descriptions. In: IWLS 2007. 16th International Workshop on Logic and Synthesis, pp. 298\u2013304 (2007)"},{"key":"11_CR10","doi-asserted-by":"crossref","unstructured":"Horeth, S., Drechsler, R.: Formal Verification of Word-Level Specifications. In: DATE 1999. Proceedings of Design Automation and Test in Europe, pp. 52\u201358 (1999)","DOI":"10.1145\/307418.307447"},{"issue":"5","key":"11_CR11","doi-asserted-by":"publisher","first-page":"356","DOI":"10.1049\/ip-cdt:20041046","volume":"151","author":"B. Alizadeh","year":"2004","unstructured":"Alizadeh, B., Navabi, Z.: Word Level Symbolic Simulation in Processor Verification. IEE Proceedings Computers and Digital Techniques Journal\u00a0151(5), 356\u2013366 (2004)","journal-title":"IEE Proceedings Computers and Digital Techniques Journal"},{"key":"11_CR12","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1109\/98.972168","volume":"8","author":"E. Grass","year":"2001","unstructured":"Grass, E., Tittelbach, K., Jagdhold, U., Troya, A., Lippert, G., Krueger, O., Lehmann, J., Maharatna, K., Fiebig, N., Dombrowski, K., Kraemer, R., Aehoenen, P.: On the Single Chip Implementation of a Hiperlan\/2 and IEEE802.11a Capable Modem. IEEE Pers. Commun.\u00a08, 48\u201357 (2001)","journal-title":"IEEE Pers. Commun."}],"container-title":["Lecture Notes in Computer Science","Automated Technology for Verification and Analysis"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-75596-8_11.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T06:25:20Z","timestamp":1619504720000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-75596-8_11"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540755951"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-75596-8_11","relation":{},"subject":[]}}