{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:56:13Z","timestamp":1725494173373},"publisher-location":"Berlin, Heidelberg","reference-count":11,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540768364"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-76837-1_24","type":"book-chapter","created":{"date-parts":[[2007,11,6]],"date-time":"2007-11-06T05:25:50Z","timestamp":1194326750000},"page":"199-208","source":"Crossref","is-referenced-by-count":2,"title":["On the Implementation of Virtual Array Using Configuration Plane"],"prefix":"10.1007","author":[{"given":"Yong-Sheng","family":"Yin","sequence":"first","affiliation":[]},{"given":"Li","family":"Li","sequence":"additional","affiliation":[]},{"given":"Ming-Lun","family":"Gao","sequence":"additional","affiliation":[]},{"given":"Gao-Ming","family":"Du","sequence":"additional","affiliation":[]},{"given":"Yu-Kun","family":"Song","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"24_CR1","unstructured":"Plessl, C., Platzner, M.: Virtualization of Hardware - Introduction and Survey. In: Proceedings of the International Conference on ERSA, pp. 63\u201369 (2004)"},{"key":"24_CR2","doi-asserted-by":"publisher","first-page":"206","DOI":"10.1109\/TVLSI.2003.821545","volume":"12","author":"S. Hauck","year":"2004","unstructured":"Hauck, S., Fry, T.W., Hosler, M.M., Kao, J.P.: The Chimaera Reconfigurable Functional Unit. IEEE Trans. on VLSI Systems.\u00a012, 206\u2013217 (2004)","journal-title":"IEEE Trans. on VLSI Systems."},{"key":"24_CR3","doi-asserted-by":"crossref","unstructured":"Cronquist, D.C., Fisher, C., Figueroa, M., Franklin, P., Ebeling, C.: Architecture Design of Reconfigurable Pipelined Datapaths. In: Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI, pp. 23\u201340 (1999)","DOI":"10.1109\/ARVLSI.1999.756035"},{"key":"24_CR4","doi-asserted-by":"crossref","unstructured":"Cadambi, S., Weener, J., Goldstein, S.C., Schmit, H., Donald, E.: Managing Pipeline-Reconfigurable FPGAs. In: ACM\/SIGDA International Symposium on FPGAs, pp. 55\u201364 (1998)","DOI":"10.1145\/275107.275120"},{"key":"24_CR5","doi-asserted-by":"publisher","first-page":"269","DOI":"10.1016\/0167-9260(96)00003-X","volume":"20","author":"F. Lorenzelli","year":"1996","unstructured":"Lorenzelli, F., Yao, K.: Integral Matrix-Based Technique for Systematic Systolic Design Integration. The VLSI Journal\u00a020, 269\u2013285 (1996)","journal-title":"The VLSI Journal"},{"key":"24_CR6","doi-asserted-by":"publisher","first-page":"129","DOI":"10.1023\/A:1008137204598","volume":"24","author":"H. Schmit","year":"2000","unstructured":"Schmit, H., Cadambi, S., Moe, M., Goldstein, S.C.: Pipeline Reconfigurable FPGAs. The Journal of VLSI Signal Processing\u00a024, 129\u2013146 (2000)","journal-title":"The Journal of VLSI Signal Processing"},{"key":"24_CR7","doi-asserted-by":"crossref","first-page":"70","DOI":"10.1109\/2.839324","volume":"33","author":"S.C. Goldstein","year":"2000","unstructured":"Goldstein, S.C, Schmit, H., Budiu, M., Cadambi, S., Moe, M., Taylor, R.R.: PipeRench: A Reconfigurable Architecture and Compiler. IEEE Computer\u00a033, 70\u201377 (2000)","journal-title":"IEEE Computer"},{"key":"24_CR8","first-page":"88","volume":"10","author":"Y.S. Yin","year":"2005","unstructured":"Yin, Y.S., Li, L., Gao, M.L.: The Reconfigurable System Based on Multi-Pipeline (in Chinese). Microelectronics & computer\u00a010, 88\u201391 (2005)","journal-title":"Microelectronics & computer"},{"key":"24_CR9","doi-asserted-by":"crossref","unstructured":"Burger, D., Austin, T.M.: The SimpelScalar Tool Set, version 2.0. University of Wisconsin-Madison Computer Sciences Department Technical Report #1342 (1997)","DOI":"10.1145\/268806.268810"},{"key":"24_CR10","unstructured":"Miyamori, T., Olukotun, K.: REMARC: Reconfigurable Multimedia Array Coprocessor. IEICE Trans. on Inf. and Syst. E82\u2013D, 389\u2013397 (1999)"},{"key":"24_CR11","doi-asserted-by":"publisher","first-page":"465","DOI":"10.1109\/12.859540","volume":"49","author":"H. Singh","year":"2000","unstructured":"Singh, H., Ming-Hau, L., Lu, G., Kurdahi, F.J., Bagherzadeh, N., Chaves Filho, E.M.: MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. IEEE Trans. on Computers.\u00a049, 465\u2013481 (2000)","journal-title":"IEEE Trans. on Computers."}],"container-title":["Lecture Notes in Computer Science","Advanced Parallel Processing Technologies"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-76837-1_24.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T06:40:52Z","timestamp":1619505652000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-76837-1_24"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540768364"],"references-count":11,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-76837-1_24","relation":{},"subject":[]}}