{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:56:12Z","timestamp":1725494172995},"publisher-location":"Berlin, Heidelberg","reference-count":4,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540768364"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-76837-1_5","type":"book-chapter","created":{"date-parts":[[2007,11,6]],"date-time":"2007-11-06T10:25:50Z","timestamp":1194344750000},"page":"14-17","source":"Crossref","is-referenced-by-count":0,"title":["The Optimum Location of Delay Latches Between Dynamic Pipeline Stages"],"prefix":"10.1007","author":[{"given":"Mahmoud Lotfi","family":"Anhar","sequence":"first","affiliation":[]},{"given":"Mohammad Ali Jabraeil","family":"Jamali","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"5_CR1","first-page":"132","volume":"61801","author":"J.H. Patel","year":"1976","unstructured":"Patel, J.H., Davidson, E.S.: Improving the Throughput of a Pipeline by Insertion of Delays. Coordinated Science Lab, University of Illinois, Urbana, Illinois\u00a061801, 132\u2013137 (1976)","journal-title":"Coordinated Science Lab, University of Illinois, Urbana, Illinois"},{"key":"5_CR2","volume-title":"Advanced Computer Architecture: Parallelism, Scalability, Programmability","author":"K. Hwang","year":"1993","unstructured":"Hwang, K.: Advanced Computer Architecture: Parallelism, Scalability, Programmability. McGraw-Hill, New York (1993)"},{"unstructured":"Davidson, E.S., Thomas, D.P., Shar, L.E., Patel, J.H.: Effective Control for Pipelined Computers. In: Proc. COMPCON, pp. 181\u2013184 (1975)","key":"5_CR3"},{"key":"5_CR4","volume-title":"The Architecture of Pipelined computers","author":"P.M. Kogge","year":"1981","unstructured":"Kogge, P.M.: The Architecture of Pipelined computers. Mc-Graw-Hill, New York (1981)"}],"container-title":["Lecture Notes in Computer Science","Advanced Parallel Processing Technologies"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-76837-1_5.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T10:41:04Z","timestamp":1619520064000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-76837-1_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540768364"],"references-count":4,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-76837-1_5","relation":{},"subject":[]}}