{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:10:42Z","timestamp":1763467842951,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540772194"},{"type":"electronic","value":"9783540772200"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-77220-0_17","type":"book-chapter","created":{"date-parts":[[2008,1,21]],"date-time":"2008-01-21T20:07:56Z","timestamp":1200946076000},"page":"147-160","source":"Crossref","is-referenced-by-count":4,"title":["Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors"],"prefix":"10.1007","author":[{"given":"Alberto","family":"Ros","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel E.","family":"Acacio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 M.","family":"Garc\u00eda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"17_CR1","doi-asserted-by":"crossref","unstructured":"Acacio, M.E., Gonz\u00e1lez, J., Garc\u00eda, J.M., Duato, J.: Owner prediction for accelerating cache-to-cache transfer misses in cc-NUMA multiprocessors. In: SC2002. High Performance Networking and Computing (November 2002)","DOI":"10.1109\/SC.2002.10063"},{"key":"17_CR2","doi-asserted-by":"crossref","unstructured":"Acacio, M.E., Gonz\u00e1lez, J., Garc\u00eda, J.M., Duato, J.: The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors. In: PACT 2002. 11th Int\u2019l Conference on Parallel Architectures and Compilation Techniques, pp. 155\u2013164 (September 2002)","DOI":"10.1109\/PACT.2002.1106014"},{"key":"17_CR3","doi-asserted-by":"crossref","unstructured":"Chang, J., Sohi, G.S.: Cooperative caching for chip multiprocessors. In: ISCA 2006. 33th Int\u2019l Symp. on Computer Architecture, pp. 264\u2013276 (June 2006)","DOI":"10.1145\/1150019.1136509"},{"key":"17_CR4","doi-asserted-by":"crossref","unstructured":"Cheng, L., Carter, J.B., Dai, D.: An adaptive cache coherence protocol optimized for producer-consumer sharing. In: HPCA-13. 13th Int\u2019l Symp. on High Performance Computer Architecture, pp. 328\u2013339 (February 2007)","DOI":"10.1109\/HPCA.2007.346210"},{"key":"17_CR5","volume-title":"Parallel Computer Architecture: A Hardware\/Software Approach","author":"D.E. Culler","year":"1999","unstructured":"Culler, D.E., Singh, J.P., Gupta, A.: Parallel Computer Architecture: A Hardware\/Software Approach. Morgan Kaufmann Publishers, Inc, San Francisco (1999)"},{"key":"17_CR6","unstructured":"Gupta, A., Weber, W.-D., Mowry, T.C.: Reducing memory traffic requirements for scalable directory-based cache coherence schemes. In: ICPP 1990. Int\u2019l Conference on Parallel Processing, pp. 312\u2013321 (August 1990)"},{"issue":"2","key":"17_CR7","doi-asserted-by":"crossref","first-page":"40","DOI":"10.1109\/2.982915","volume":"35","author":"C.J. Hughes","year":"2002","unstructured":"Hughes, C.J., Pai, V.S., Ranganathan, P., Adve, S.V.: RSIM: Simulating shared-memory multiprocessors with ILP processors. IEEE Computer\u00a035(2), 40\u201349 (2002)","journal-title":"IEEE Computer"},{"key":"17_CR8","unstructured":"Martin, M.M.: Token Coherence. PhD thesis, University of Wisconsin-Madison (December 2003)"},{"key":"17_CR9","doi-asserted-by":"crossref","unstructured":"Martin, M.M., Hill, M.D., Wood, D.A.: Token coherence: Decoupling performance and correctness. In: ISCA 2003. 30th Int\u2019l Symp. on Computer Architecture, pp. 182\u2013193 (June 2003)","DOI":"10.1145\/859618.859640"},{"key":"17_CR10","doi-asserted-by":"crossref","unstructured":"Martin, M.M., Sorin, D.J., Ailamaki, A., Alameldeen, A.R., Dickson, R.M., Mauer, C.J., Moore, K.E., Plakal, M., Hill, M.D., Wood, D.A.: Timestamp snooping: An approach for extending SMPs. In: ASPLOS IX. 9th Int\u2019l Conference on Architectural Support for Programming Languages and Operating Systems, pp. 25\u201336 (November 2000)","DOI":"10.1145\/378993.378998"},{"key":"17_CR11","doi-asserted-by":"crossref","unstructured":"Martin, M.M., Sorin, D.J., Hill, M.D., Wood, D.A.: Bandwidth adaptive snooping. In: HPCA-8. 8th Int\u2019l Symp. on High-Performance Computer Architecture, pp. 251\u2013262 (January 2002)","DOI":"10.1109\/HPCA.2002.995715"},{"key":"17_CR12","doi-asserted-by":"crossref","unstructured":"Nanda, A.K., Nguyen, A.-T., Michael, M.M., Joseph, D.J.: High-throughput coherence controllers. In: HPCA-6. 6th Int\u2019l Symp. on High-Performance Computer Architecture, pp. 145\u2013155 (January 2000)","DOI":"10.1109\/HPCA.2000.824346"},{"key":"17_CR13","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"crossref","first-page":"582","DOI":"10.1007\/11549468_65","volume-title":"Euro-Par 2005 Parallel Processing","author":"A. Ros","year":"2005","unstructured":"Ros, A., Acacio, M.E., Garc\u00eda, J.M.: A novel lightweight directory architecture for scalable shared-memory multiprocessors. In: Cunha, J.C., Medeiros, P.D. (eds.) Euro-Par 2005. LNCS, vol.\u00a03648, pp. 582\u2013591. Springer, Heidelberg (2005)"},{"key":"17_CR14","doi-asserted-by":"crossref","unstructured":"Ros, A., Acacio, M.E., Garc\u00eda, J.M.: An efficient cache design for scalable glueless shared-memory multiprocessors. In: ACM Int\u2019l Conference on Computing Frontiers, pp. 321\u2013330 (2006)","DOI":"10.1145\/1128022.1128065"},{"key":"17_CR15","doi-asserted-by":"crossref","unstructured":"Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 programs: Characterization and methodological considerations. In: ISCA 1995. 22nd Int\u2019l Symp. on Computer Architecture, pp. 24\u201336 (June 1995)","DOI":"10.1145\/225830.223990"},{"issue":"1","key":"17_CR16","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1145\/216585.216588","volume":"23","author":"W. Wulf","year":"1995","unstructured":"Wulf, W., McKee, S.: Hitting the memory wall: Implications of the obvious. Computer Architecture News\u00a023(1), 20\u201324 (1995)","journal-title":"Computer Architecture News"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing \u2013 HiPC 2007"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-77220-0_17.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,25]],"date-time":"2025-01-25T23:52:44Z","timestamp":1737849164000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-77220-0_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540772194","9783540772200"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-77220-0_17","relation":{},"subject":[]}}