{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T01:55:32Z","timestamp":1725501332895},"publisher-location":"Berlin, Heidelberg","reference-count":16,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540775591"},{"type":"electronic","value":"9783540775607"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-77560-7_18","type":"book-chapter","created":{"date-parts":[[2008,1,17]],"date-time":"2008-01-17T01:13:02Z","timestamp":1200532382000},"page":"258-272","source":"Crossref","is-referenced-by-count":5,"title":["Turbo-ROB: A Low Cost Checkpoint\/Restore Accelerator"],"prefix":"10.1007","author":[{"given":"Patrick","family":"Akl","sequence":"first","affiliation":[]},{"given":"Andreas","family":"Moshovos","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"18_CR1","doi-asserted-by":"crossref","unstructured":"Akkary, H., Rajwar, R., Srinivasan, S.: An Analysis of Resource Efficient Checkpoint Architecture. ACM Transactions on Architecture and Code Optimization (TACO)\u00a01(4) (December 2004)","DOI":"10.1145\/1044823.1044826"},{"key":"18_CR2","unstructured":"Akkary, H., Rajwar, R., Srinivasan, S.: Checkpoint Processing and Recovery: Towards Scalable Instruction Window Processors. In: Proceedings of the 36 th Annual IEEE\/ACM International Symposium on Microarchitecture (November 2003)"},{"key":"18_CR3","doi-asserted-by":"crossref","unstructured":"Aragon, J.L., Gonzalez, J., Gonzalez, A., Smith, J.E.: Dual Path Instruction Processing. In: Proceedings of the 16 th International Conference on Supercomputing, pp. 220\u2013229 (June 2002)","DOI":"10.1145\/514191.514223"},{"key":"18_CR4","doi-asserted-by":"crossref","unstructured":"Burger, D., Austin, T.: The Simplescalar Tool Set v2.0, Technical Report UW-CS-97-1342., Computer Sciences Department, University of Wisconsin-Madison (June 1997)","DOI":"10.1145\/268806.268810"},{"key":"18_CR5","doi-asserted-by":"crossref","unstructured":"Cristal, A., Ortega, D., Llosa, J., Valero, M.: Kilo-Instruction Processors. In: Proceedings The 5 th International Symposium on High Performance Computing (ISHPC-V) (October 2003)","DOI":"10.1007\/978-3-540-39707-6_2"},{"key":"18_CR6","doi-asserted-by":"crossref","unstructured":"Grunwald, D., Klauser, A., Manne, S., Pleszkun, A.: Confidence Estimation for Speculation Control. In: Proceedings of the 25 th Annual International Symposium on Computer Architecture (June 1998)","DOI":"10.1109\/ISCA.1998.694768"},{"key":"18_CR7","doi-asserted-by":"crossref","unstructured":"Hwu, W.W., Patt, Y.N.: Checkpoint Repair for Out-of-Order Execution Machines. In: Proceedings of the 14 th Annual Symposium on Computer Architecture (June 1987)","DOI":"10.1145\/30350.30353"},{"key":"18_CR8","doi-asserted-by":"crossref","unstructured":"Jacobsen, E., Rotenberg, E., Smith, J.E.: Assigning Confidence to Conditional Branch Predictions. In: Proceedings of the 29 th Annual International Symposium on Microarchitecture (Decmber 1996)","DOI":"10.1109\/MICRO.1996.566457"},{"key":"18_CR9","unstructured":"Jimenez, D.A., Lin, C.: Composite Confidence Estimators for Enhanced Speculation Control, Technical Report TR-02-14, Department of Computer Sciences, The University of Texas at Austin (January 2002)"},{"key":"18_CR10","doi-asserted-by":"crossref","unstructured":"Manne, S., Klauser, A., Grunwald, D.: Pipeline Gating: Speculation Control for Energy Reduction. In: Proceedings of the 25 th Annual International Symposium on Computer Architecture (June 1998)","DOI":"10.1145\/279361.279377"},{"key":"18_CR11","doi-asserted-by":"crossref","unstructured":"Moshovos, A.: Checkpointing Alternatives for High Performance, Power-Aware Processors. In: Proceedings of the IEEE International Symposium Low Power Electronic Devices and Design (ISLPED) (August 2003)","DOI":"10.1145\/871506.871585"},{"key":"18_CR12","doi-asserted-by":"crossref","unstructured":"Safi, E., Akl, P., Moshovos, A., Veneris, A., Arapoyianni, A.: On the Latency, Energy and Area of Superscalar Renaming Tables. In: Proceedings of the IEEE\/ACM International Symposium on Low Power Electronics and Devices (August 2007)","DOI":"10.1145\/1283780.1283863"},{"key":"18_CR13","doi-asserted-by":"crossref","unstructured":"Smith, J., Pleszkun, A.: Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers\u00a037(5) (May 1988)","DOI":"10.1109\/12.4607"},{"key":"18_CR14","doi-asserted-by":"crossref","unstructured":"Sohi, G.S.: Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers. IEEE Transactions on Computers\u00a0 (March 1990)","DOI":"10.1109\/12.48865"},{"key":"18_CR15","doi-asserted-by":"crossref","unstructured":"Yeager, K.C.: The MIPS R10000 Superscalar Microprocessor. IEEE MICRO\u00a0 (1996)","DOI":"10.1109\/40.491460"},{"key":"18_CR16","doi-asserted-by":"crossref","unstructured":"Zhou, P., Onder, S., Carr, S.: Fast Branch Misprediction Recovery in Out-of-Order Superscalar Processors. In: Proceedings of the International Conference on Supercomputing (June 2005)","DOI":"10.1145\/1088149.1088156"}],"container-title":["Lecture Notes in Computer Science","High Performance Embedded Architectures and Compilers"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-77560-7_18.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T06:44:25Z","timestamp":1619505865000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-77560-7_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540775591","9783540775607"],"references-count":16,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-77560-7_18","relation":{},"subject":[]}}