{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,26]],"date-time":"2025-01-26T05:51:24Z","timestamp":1737870684994,"version":"3.33.0"},"publisher-location":"Berlin, Heidelberg","reference-count":22,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540777038"},{"type":"electronic","value":"9783540777045"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-77704-5_17","type":"book-chapter","created":{"date-parts":[[2008,1,19]],"date-time":"2008-01-19T01:28:36Z","timestamp":1200706116000},"page":"199-210","source":"Crossref","is-referenced-by-count":0,"title":["The Bandwidth Expansion Effectiveness of Cache Levels Block Prefetch"],"prefix":"10.1007","author":[{"given":"Youngkwan","family":"Ju","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bongyong","family":"Uh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sukil","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"17_CR1","volume-title":"Introduction to Parallel Computing","author":"A. Grama","year":"2003","unstructured":"Grama, A., Gupta, A., Karapis, G., Kumar, V.: Introduction to Parallel Computing, 2nd edn. Addison Wesley, Reading (2003)","edition":"2"},{"key":"17_CR2","doi-asserted-by":"crossref","unstructured":"Fritts, J.: Multi-Level Memory Prefetching for Media and Streaming Processing. In: Proceedings International Conference on Multimedia and Expo (2002)","DOI":"10.1109\/ICME.2002.1035522"},{"key":"17_CR3","unstructured":"Bear, J.L., Wang, W.H.: Architectural Choices for Multi-level Cache Hierarchies. In: Proceedings 16th international Conference on Parallel Processing, pp. 258\u2013256 (1987)"},{"issue":"9","key":"17_CR4","first-page":"573","volume":"29","author":"H.J. Moon","year":"2002","unstructured":"Moon, H.J., Jeon, J.N., Kim, S.: Design of A Media Processor Equipped with Dual Cache. Journal Korean Institution Science Society\u00a029(9), 573\u2013581 (2002)","journal-title":"Journal Korean Institution Science Society"},{"key":"17_CR5","doi-asserted-by":"crossref","unstructured":"Gaddis, N.B., Butler, J.R., Kumar, A., Queen, W.J.: A 56-entry instruction reorder buffer, Solid-State Circuits Conference. In: IEEE International Digest of Technical Papers. 43rd ISSCC, pp. 212\u2013213 (February 1996)","DOI":"10.1109\/ISSCC.1996.488575"},{"key":"17_CR6","doi-asserted-by":"crossref","unstructured":"Joseph, D., Grunwald, D.: Prefetching Using Markov Predictors. In: Proceedings 24th Inl. Symp. Computer Architecture, pp. 252\u2013263 (June 1997)","DOI":"10.1145\/264107.264207"},{"key":"17_CR7","doi-asserted-by":"crossref","unstructured":"Zhang, X., Lee, H.S.: A hardware-based cache pollution filtering mechanism for aggressive prefetches. In: Proceedings 2003 International Conference on Parallel Processing, pp. 286\u2013293 (October 6-9, 2003)","DOI":"10.1109\/ICPP.2003.1240591"},{"issue":"2","key":"17_CR8","first-page":"7","volume":"11","author":"A. Smith","year":"1997","unstructured":"Smith, A.: Sequential Program Prefetching in Memory Hierarchies. IEEE Computer\u00a011(2), 7\u201321 (1997)","journal-title":"IEEE Computer"},{"key":"17_CR9","doi-asserted-by":"crossref","unstructured":"Jouppi, N.P.: Improving Direct-mapped Cache Performance by the Addition of a Small Fully associative Cache and Prefetch Buffers. In: Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 364\u2013373 (May 1990)","DOI":"10.1145\/325096.325162"},{"issue":"3","key":"17_CR10","doi-asserted-by":"publisher","first-page":"73","DOI":"10.1109\/40.768506","volume":"19","author":"T. Horel","year":"1999","unstructured":"Horel, T., Lauterbach, G.: UltraSPARC-III: Designing Third-generation 64-bit Performance. IEEE Micro\u00a019(3), 73\u201385 (1999)","journal-title":"IEEE Micro"},{"issue":"5","key":"17_CR11","doi-asserted-by":"publisher","first-page":"609","DOI":"10.1109\/12.381947","volume":"44","author":"T.F. Chen","year":"1995","unstructured":"Chen, T.F., Baer, J.L.: Effective Hardware-Based Data Prefetching for High Performance Processors. IEEE Transactions on Computers\u00a044(5), 609\u2013623 (1995)","journal-title":"IEEE Transactions on Computers"},{"issue":"11","key":"17_CR12","first-page":"658","volume":"31","author":"Y.S. Jeon","year":"2004","unstructured":"Jeon, Y.S., Moon, H.J., Jeon, J.N., Kim, S.: A Hardware Cache Prefetching Scheme for Multimedia Data with Intermittently Irregular Strides. KIPS Architecture\u00a031(11), 658\u2013672 (2004)","journal-title":"KIPS Architecture"},{"issue":"1","key":"17_CR13","first-page":"25","volume":"47","author":"K.K. Chan","year":"1996","unstructured":"Chan, K.K., Hay, C.C., Keller, J.R., Kurpanek, G.P., Schumacher, F.X., Zheng, J.: Design of the HP PA 7200 CPU. Hewlett-Packard Journal\u00a047(1), 25\u201333 (1996)","journal-title":"Hewlett-Packard Journal"},{"key":"17_CR14","unstructured":"Pentium Processor User\u2019s Manual, Vol.1, Pentium Processor Databook, Intel (1993)"},{"key":"17_CR15","unstructured":"IA-32 Intel Architecture Software Developer s Manual, Vol.1, Basic Architecture, Intel (2004)"},{"key":"17_CR16","unstructured":"Denamn, M.: PowerPC 604. Hot Chips VI, 193\u2013200 (1994)"},{"key":"17_CR17","doi-asserted-by":"crossref","unstructured":"Mutlu, O., Kim, H.S., Armstrong, D.N., Patt, Y.N.: Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. In: SBAC-PAD 2004. 16th Symposium Computer Architecture and High Performance Computing, October 27-29, 2004, pp. 2\u20139 (2004)","DOI":"10.1109\/SBAC-PAD.2004.11"},{"key":"17_CR18","unstructured":"Lee, J.S., Hong, W.K., Kim, S.D.: Design and Evaluation of On-Chip Cache Compression Technology. In: Proceedings the 17th IEEE International Conference on Computer Design, pp. 184\u2013191 (1999)"},{"key":"17_CR19","doi-asserted-by":"crossref","unstructured":"Rivers, J.A., Tyson, G.S., Davidson, E.S., Austin, T.M.: On High-Bandwidth Data Cache Design for Multi-Issue Processors. In: Proceedings of the 30th Annual International Symposium on Micro architecture, pp. 46\u201356 (December 1997)","DOI":"10.1109\/MICRO.1997.645796"},{"issue":"5","key":"17_CR20","first-page":"607","volume":"5","author":"J.H. Lee","year":"2003","unstructured":"Lee, J.H., et al.: An Intelligent Cache System with Hardware Prefetching for High Performance. IEEE Transactions on Computers\u00a05(5), 607\u2013617 (2003)","journal-title":"IEEE Transactions on Computers"},{"key":"17_CR21","doi-asserted-by":"publisher","first-page":"563","DOI":"10.1109\/TPDS.2003.1206504","volume":"14","author":"Y. Solihin","year":"2003","unstructured":"Solihin, Y., Lee, J., Torrellas, J.: Correlation prefetching with a user-level memory thread. IEEE Transactions on Parallel and Distributed Systems\u00a014, 563\u2013580 (2003)","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"17_CR22","doi-asserted-by":"crossref","unstructured":"Srivastava, A., Eustace, A.: ATOM: A System for Building Customized Program Analysis Tools. In: Proceedings ACM SIGPLAN 1994, pp. 196\u2013205 (1994)","DOI":"10.1145\/178243.178260"}],"container-title":["Lecture Notes in Computer Science","High-Performance Computing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-77704-5_17.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,25]],"date-time":"2025-01-25T21:45:04Z","timestamp":1737841504000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-77704-5_17"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540777038","9783540777045"],"references-count":22,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-77704-5_17","relation":{},"subject":[]}}