{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T02:04:06Z","timestamp":1725501846203},"publisher-location":"Berlin, Heidelberg","reference-count":18,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540779643"},{"type":"electronic","value":"9783540779667"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1007\/978-3-540-77966-7_7","type":"book-chapter","created":{"date-parts":[[2008,2,1]],"date-time":"2008-02-01T08:59:24Z","timestamp":1201856364000},"page":"34-50","source":"Crossref","is-referenced-by-count":0,"title":["Reactivity in SystemC Transaction-Level Models"],"prefix":"10.1007","author":[{"given":"Frederic","family":"Doucet","sequence":"first","affiliation":[]},{"given":"R. K.","family":"Shyamasundar","sequence":"additional","affiliation":[]},{"given":"Ingolf H.","family":"Kr\u00fcger","sequence":"additional","affiliation":[]},{"given":"Saurabh","family":"Joshi","sequence":"additional","affiliation":[]},{"given":"Rajesh K.","family":"Gupta","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"7_CR1","volume-title":"System Design with SystemC","author":"T. Groetker","year":"2002","unstructured":"Groetker, T., Liao, S., Martin, G., Swan, S.: System Design with SystemC. Kluwer Academic Publishers, Dordrecht (2002)"},{"key":"7_CR2","volume-title":"The Foundations of Esterel","author":"G. Berry","year":"2000","unstructured":"Berry, G.: The Foundations of Esterel. MIT Press, Cambridge (2000)"},{"doi-asserted-by":"crossref","unstructured":"Liao, S., Tjiang, S., Gupta, R.: An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment. In: Proc. of the Design Automation Conf. (1997)","key":"7_CR3","DOI":"10.1109\/DAC.1997.597119"},{"unstructured":"Marschner, E., Deadman, B., Martin, G.: IP Reuse Hardening via Embedded Sugar Assertions. In: Proc. of the Int. Workshop on IP SOC Design (2002)","key":"7_CR4"},{"doi-asserted-by":"crossref","unstructured":"Balarin, F., Passerone, R.: Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation. In: Proc. Design Automation and Test in Europe Conf. (2006)","key":"7_CR5","DOI":"10.1109\/DATE.2006.243899"},{"doi-asserted-by":"crossref","unstructured":"Berry, G., Ramesh, S., Shyamasundar, R.K.: Communicating Reactive Processes. In: Proc. of the Symposium on Principles of Programming Languages (1993)","key":"7_CR6","DOI":"10.1145\/158511.158526"},{"key":"7_CR7","doi-asserted-by":"publisher","first-page":"172","DOI":"10.1109\/92.285744","volume":"2","author":"A. Seawright","year":"1994","unstructured":"Seawright, A., Brewer, F.: Clairvoyant: A Synthesis System for Production-based Specifications. IEEE Trans. on Very Large Scale Integration (VLSI) Systems\u00a02, 172\u2013185 (1994)","journal-title":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems"},{"key":"7_CR8","doi-asserted-by":"publisher","first-page":"84","DOI":"10.1109\/MDT.2002.1018137","volume":"19","author":"R. Siegmund","year":"2002","unstructured":"Siegmund, R., Muller, D.: Automatic Synthesis of Communication Controller Hardware from Protocol Specification. IEEE Design and Test of Computer\u00a019, 84\u201395 (2002)","journal-title":"IEEE Design and Test of Computer"},{"doi-asserted-by":"crossref","unstructured":"Oliveira, M., Hu, A.: High-level Specification and Automatic Generation of IP Interface Monitors. In: Proc. of the Design Automation Conf. (2002)","key":"7_CR9","DOI":"10.1145\/513950.513952"},{"unstructured":"Shimizu, K.: Writing, Verifying, and Exploiting Formal Specifications for Hardware Designs. PhD thesis, Stanford University (2002)","key":"7_CR10"},{"doi-asserted-by":"crossref","unstructured":"Zhu, Q., Oishi, R., Hasegawa, T., Nakata, T.: System-on-Chip Validation using UML and CWL. In: Proc. of the Int. Conf. on Hardware-Software Codesign and System Synthesis (2004)","key":"7_CR11","DOI":"10.1145\/1016720.1016745"},{"doi-asserted-by":"crossref","unstructured":"Abarbanel, Y., Beer, I., Glushovsky, L., Keidar, S., Wolfsthal, Y.: FoCs: Automatic Generation of Simulation Checkers from Formal Specifications. In: Proc. of the Int. Conf. on Computer Aided Verification. pp. 538\u2013542 (2000)","key":"7_CR12","DOI":"10.1007\/10722167_40"},{"key":"7_CR13","first-page":"19","volume-title":"Proc. of the Int. Conf. on Hardware\/Software Codesign and System Synthesis","author":"L. Cai","year":"2003","unstructured":"Cai, L., Gajski, D.: Transaction-level Modeling: an Overview. In: Proc. of the Int. Conf. on Hardware\/Software Codesign and System Synthesis, pp. 19\u201324. ACM Press, New York (2003)"},{"key":"7_CR14","doi-asserted-by":"publisher","first-page":"57","DOI":"10.1109\/TVLSI.2005.863187","volume":"14","author":"A. Habibi","year":"2006","unstructured":"Habibi, A., Tahar, S.: Design and Verification of SystemC Transaction-level Models. IEEE Transactions on Very Large Scale Integration Systems\u00a014, 57\u201368 (2006)","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"doi-asserted-by":"crossref","unstructured":"Moy, M., Maraninchi, F., Maillet-Contoz, L.: LusSy: A Toolbox for the Analysis of System-on-a-Chip at the Transactional Level. In: Proc. of the Int. Conf. on Application of Concurrency to System Design (2005)","key":"7_CR15","DOI":"10.1109\/ACSD.2005.23"},{"unstructured":"Kroening, D., Sharygina, N.: Formal Verification of SystemC by Automatic Hardware\/Software Partitioning. In: Proc. of the Int. Conf. on Formal Methods and Models for Codesign (2007)","key":"7_CR16"},{"key":"7_CR17","series-title":"Series in Computer Science","volume-title":"Communicating Sequential Processes","author":"C.A.R. Hoare","year":"1985","unstructured":"Hoare, C.A.R.: Communicating Sequential Processes. Series in Computer Science. Prentice-Hall International, Englewood Cliffs (1985)"},{"doi-asserted-by":"crossref","unstructured":"Shyamasundar, R., Doucet, F., Gupta, R., Kr\u00fcger, I.H.: Compositional Reactive Semantics of SystemC and Verification in RuleBase. In: Proc. of the Workshop on Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems (2007)","key":"7_CR18","DOI":"10.1007\/978-1-4020-6254-4_18"}],"container-title":["Lecture Notes in Computer Science","Hardware and Software: Verification and Testing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-77966-7_7.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,4,27]],"date-time":"2021-04-27T10:57:28Z","timestamp":1619521048000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-77966-7_7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"ISBN":["9783540779643","9783540779667"],"references-count":18,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-77966-7_7","relation":{},"subject":[]}}