{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T03:18:17Z","timestamp":1742959097878,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540897392"},{"type":"electronic","value":"9783540897408"}],"license":[{"start":{"date-parts":[[2008,1,1]],"date-time":"2008-01-01T00:00:00Z","timestamp":1199145600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008]]},"DOI":"10.1007\/978-3-540-89740-8_5","type":"book-chapter","created":{"date-parts":[[2008,11,27]],"date-time":"2008-11-27T08:14:24Z","timestamp":1227773664000},"page":"64-79","source":"Crossref","is-referenced-by-count":0,"title":["Register Bank Assignment for Spatially Partitioned Processors"],"prefix":"10.1007","author":[{"given":"Behnam","family":"Robatmili","sequence":"first","affiliation":[]},{"given":"Katherine","family":"Coons","sequence":"additional","affiliation":[]},{"given":"Doug","family":"Burger","sequence":"additional","affiliation":[]},{"given":"Kathryn S.","family":"McKinley","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"5_CR1","doi-asserted-by":"crossref","unstructured":"Bernstein, D., Golumbic, M., Mansour, Y., Pinter, R., Goldin, D., Nahshon, I., Krawczyk, H.: Spill code minimization techniques for optimizing compliers. In: ACM SIGPLAN Symposium on Interpreters and Interpretive Techniques, pp. 258\u2013263 (1989)","DOI":"10.1145\/73141.74841"},{"key":"5_CR2","unstructured":"Brasier, T.S., Sweany, P.H., Beaty, S.J., Carr, S.: CRAIG: a practical framework for combining instruction scheduling and register assignment. In: Parallel Architectures and Compilation Techniques, pp. 11\u201318 (1995)"},{"key":"5_CR3","doi-asserted-by":"crossref","unstructured":"Briggs, P., Cooper, K.D., Torczon, L.: Improvements to graph coloring register allocation. In: ACM Transactions on Programming Languages and Systems, May 1994, vol.\u00a016(3), pp. 428\u2013455 (1994)","DOI":"10.1145\/177492.177575"},{"key":"5_CR4","doi-asserted-by":"crossref","unstructured":"Chaitin, G.: Register allocation and spilling via graph coloring. In: ACM SIGPLAN Symposium on Compiler Construction, pp. 98\u2013105 (1982)","DOI":"10.1145\/800230.806984"},{"key":"5_CR5","doi-asserted-by":"crossref","unstructured":"Chow, F.C., Hennessy, J.L.: Priority-based coloring approach to register allocation. In: ACM Transactions on Programming Languages and Systems, vol.\u00a012, pp. 501\u2013536 (1990)","DOI":"10.1145\/88616.88621"},{"key":"5_CR6","doi-asserted-by":"crossref","unstructured":"Coons, K., Chen, X., Kushwaha, S., Burger, D., McKinley, K.S.: A spatial path scheduling algorithm for edge architectures. In: ACM Conference on Architecture Support for Programming Languages and Operating Systems, pp. 129\u2013140 (2006)","DOI":"10.1145\/1168857.1168875"},{"key":"5_CR7","unstructured":"EEMBC. Embedded microprocessor benchmark consortium, \n                  \n                    http:\/\/www.eembc.org\/"},{"key":"5_CR8","unstructured":"Ellis, J.: A Compiler for VLIW Architecture. PhD thesis, Yale University (1984)"},{"key":"5_CR9","doi-asserted-by":"crossref","unstructured":"Farkas, K.L., Chow, P., Jouppi, N.P., Vranesic, Z.: The multicluster architecture: Reducing processor cycle time through partitioning. In: ACM\/IEEE Symposium on Microarchitecture, pp. 327\u2013356 (1997)","DOI":"10.1109\/MICRO.1997.645806"},{"key":"5_CR10","doi-asserted-by":"crossref","unstructured":"Hiser, J., Carr, S., Sweany, P., Beaty, S.J.: Register assignment for software pipelining with partitioned register banks. In: International Parallel and Distributed Processing Symposium, pp. 211\u2013217 (2000)","DOI":"10.1109\/IPDPS.2000.845983"},{"key":"5_CR11","doi-asserted-by":"crossref","unstructured":"Janssen, J., Corporaal, H.: Partitioned register files for TTAs. In: ACM\/IEEE Symposium on Micorarchitecture, December 1995, pp. 301\u2013312 (1995)","DOI":"10.1109\/MICRO.1995.476840"},{"key":"5_CR12","doi-asserted-by":"crossref","unstructured":"Kailas, K., Ebcioglu, K., Agrawala, A.: Cars: A new code generation framework for clustered ILP processors. In: Conference on High Performance Computer Architecture, pp. 133\u2013143 (2001)","DOI":"10.1109\/HPCA.2001.903258"},{"key":"5_CR13","doi-asserted-by":"crossref","unstructured":"Maher, B., Smith, A., Burger, D., McKinley, K.S.: Merging head and tail duplication for convergent hyperblock formation. In: ACM\/IEEE International Symposium on Microarchitecture, pp. 65\u201376 (2006)","DOI":"10.1109\/MICRO.2006.34"},{"key":"5_CR14","doi-asserted-by":"crossref","unstructured":"Poletto, M., Sarkar, V.: Linear scan register allocation. In: ACM Transactions on Programming Languages and Systems, Spetember 1999, vol.\u00a021, pp. 895\u2013913 (1999)","DOI":"10.1145\/330249.330250"},{"key":"5_CR15","doi-asserted-by":"crossref","unstructured":"Smith, A., Burrill, J., Gibson, J., Maher, B., Nethercote, N., Yoder, B., Burger, D.C., McKinley, K.S.: Compiling for EDGE architectures. In: International Conference on Code Generation and Optimization, pp. 185\u2013195 (2006)","DOI":"10.1109\/CGO.2006.10"},{"key":"5_CR16","unstructured":"SPEC2000CPU. The standard performance evaluation corporation (SPEC), \n                  \n                    http:\/\/www.spec.org\/"},{"key":"5_CR17","doi-asserted-by":"crossref","unstructured":"Taylor, M.B., Agarwal, A.: Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ILP and streams. In: ACM SIGARCH International Symposium on Computer Architecture, pp. 2\u201313 (2004)","DOI":"10.1145\/1028176.1006733"},{"key":"5_CR18","doi-asserted-by":"crossref","unstructured":"Traub, O., Holloway, G., Smith, M.D.: Quality and speed in linear-scan register allocation. In: ACM SIGPLAN Conference on Programming Language Design and Implementation, June 1998, pp. 895\u2013913 (1998)","DOI":"10.1145\/277650.277714"},{"key":"5_CR19","doi-asserted-by":"crossref","unstructured":"Warter, N.J.: Reverse if-conversion. In: ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 290\u2013299 (1993)","DOI":"10.1145\/155090.155118"},{"key":"5_CR20","unstructured":"Yoder, B., Burrill, J., McDonald, R., Bush, K.B., Coons, K., Gebhart, M., Govindan, S., Maher, B., Nagarajan, R., Robatmili, B., Sankaralingam, K., Sharif, S., Smith, A.: Software infrastructure and tools for the TRIPS prototype. In: Third Annual Workshop on Modeling, Benchmarking and Simulation (2007)"}],"container-title":["Lecture Notes in Computer Science","Languages and Compilers for Parallel Computing"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-89740-8_5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,4]],"date-time":"2019-03-04T00:49:43Z","timestamp":1551660583000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-89740-8_5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008]]},"ISBN":["9783540897392","9783540897408"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-89740-8_5","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2008]]}}}