{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T07:40:04Z","timestamp":1725522004465},"publisher-location":"Berlin, Heidelberg","reference-count":34,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540898931"},{"type":"electronic","value":"9783540898948"}],"license":[{"start":{"date-parts":[[2008,1,1]],"date-time":"2008-01-01T00:00:00Z","timestamp":1199145600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008]]},"DOI":"10.1007\/978-3-540-89894-8_33","type":"book-chapter","created":{"date-parts":[[2008,12,16]],"date-time":"2008-12-16T10:22:24Z","timestamp":1229422944000},"page":"365-377","source":"Crossref","is-referenced-by-count":0,"title":["Scalable Multi-cores with Improved Per-core Performance Using Off-the-critical Path Reconfigurable Hardware"],"prefix":"10.1007","author":[{"given":"Tameesh","family":"Suri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aneesh","family":"Aggarwal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"33_CR1","doi-asserted-by":"crossref","unstructured":"Athanas, P., et al.: Processor reconfiguration through instruction-set metamorphosis. IEEE Computer\u00a026(3) (1995)","DOI":"10.1109\/2.204677"},{"key":"33_CR2","doi-asserted-by":"crossref","unstructured":"Bracy, A., et al.: Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth. In: Proc. MICRO (2004)","DOI":"10.1109\/MICRO.2004.15"},{"key":"33_CR3","doi-asserted-by":"crossref","unstructured":"Bracy, A., et al.: Serialization-Aware Mini-Graphs: Performance with Fewer Resources. In: Proc. MICRO (2006)","DOI":"10.1109\/MICRO.2006.45"},{"issue":"4","key":"33_CR4","doi-asserted-by":"publisher","first-page":"62","DOI":"10.1109\/2.839323","volume":"33","author":"T. Callahan","year":"2000","unstructured":"Callahan, T., et al.: The garp architecture and c compiler. IEEE Computer\u00a033(4), 62\u201369 (2000)","journal-title":"IEEE Computer"},{"key":"33_CR5","doi-asserted-by":"crossref","unstructured":"Chou, Y., et al.: Piperench implementation of the instruction path coprocessor. In: Proc. MICRO (2000)","DOI":"10.1145\/360128.360144"},{"key":"33_CR6","doi-asserted-by":"crossref","unstructured":"Clark, N., et al.: An architecture framework for transparent instruction set customization in embedded processors. In: Proc. ISCA (2005)","DOI":"10.1109\/ISCA.2005.9"},{"key":"33_CR7","doi-asserted-by":"crossref","unstructured":"Clark, N., et al.: Processor acceleration through automated instruction-set customization. In: Proc. MICRO (2003)","DOI":"10.1109\/MICRO.2003.1253189"},{"key":"33_CR8","doi-asserted-by":"crossref","unstructured":"Clark, N., et al.: Application Specific Processing on a General Purpose Core via Transparent Instruction Set Customization. In: Proc. MICRO (2004)","DOI":"10.1109\/MICRO.2004.5"},{"key":"33_CR9","doi-asserted-by":"crossref","unstructured":"Corliss, M.L., et al.: DISE: A Programmable Macro Engine for Customizing Applications. In: Proc. ISCA (2003)","DOI":"10.1145\/859618.859660"},{"key":"33_CR10","doi-asserted-by":"crossref","unstructured":"Fahs, B., et al.: Performance characterization of a hardware mechanism for dynamic optimization. In: Proc. MICRO (2001)","DOI":"10.1109\/MICRO.2001.991102"},{"key":"33_CR11","unstructured":"Guthaus, M.R., et al.: MiBench: A free, commercially representative embedded benchmark suite. Work. Workload Characterization (2001)"},{"key":"33_CR12","doi-asserted-by":"crossref","unstructured":"Hammond, L., et al.: A Single-Chip Multiprocessor. IEEE Computer\u00a030(9) (September 1997)","DOI":"10.1109\/2.612253"},{"key":"33_CR13","doi-asserted-by":"crossref","unstructured":"Hauck, S., et al.: The chimaera reconfigurable functional unit. In: Proc. FCCM (1997)","DOI":"10.1109\/FPGA.1997.624608"},{"key":"33_CR14","unstructured":"Hu, S., et al.: An Approach for Implementing Efficient Superscalar CISC Processors. In: Proc. HPCA (2006)"},{"key":"33_CR15","unstructured":"Hu, S., Smith, J.: Using Dynamic Binary Translation to Fuse Dependent Instructions. In: Int. Symp. on CGO (2004)"},{"issue":"3","key":"33_CR16","doi-asserted-by":"publisher","first-page":"231","DOI":"10.1007\/BF01212870","volume":"9","author":"C. Iseli","year":"1995","unstructured":"Iseli, C., Sanchez, E.: Spyder: a sure (superscalar and reconfigurable) processor. Journal of Supercomputing\u00a09(3), 231\u2013252 (1995)","journal-title":"Journal of Supercomputing"},{"key":"33_CR17","unstructured":"Intel Corporation, Mobile Intel Pentium 4 M-Processor Datasheet (June 2003), http:\/\/www.intel.com\/design\/mobile\/datashts\/250686.htm"},{"key":"33_CR18","doi-asserted-by":"crossref","unstructured":"Jacob, J.A., Chow, P.: Memory interfacing an instruction specification for reconfigurable processors. In: Symp. FPGAs (1999)","DOI":"10.1145\/296399.296446"},{"key":"33_CR19","doi-asserted-by":"crossref","unstructured":"Kim, I., Lipasti, M.: Macro-op Scheduling: Relaxing Scheduling Loop Constraints. In: Proc. MICRO (2003)","DOI":"10.1109\/MICRO.2003.1253202"},{"key":"33_CR20","doi-asserted-by":"crossref","unstructured":"Kumar, R., et al.: Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. In: Proc. ISCA (2005)","DOI":"10.1145\/1080695.1070004"},{"key":"33_CR21","unstructured":"Lee, C., et al.: MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In: Proc. MICRO (1997)"},{"key":"33_CR22","doi-asserted-by":"crossref","unstructured":"Lotz, J., et al.: A Quad-Issue Out-of-Order RISC CPU. In: Proc. Int\u2019l. Solid-State Circuits Conf. (1996)","DOI":"10.1109\/ISSCC.1996.488574"},{"issue":"2","key":"33_CR23","first-page":"389","volume":"E82-D","author":"T. Miyamori","year":"1999","unstructured":"Miyamori, T., Olukotun, K.: Remarc: Reconfigurable multimedia array co-processor. IEICE Trans. on information and systems\u00a0E82-D(2), 389\u2013397 (1999)","journal-title":"IEICE Trans. on information and systems"},{"key":"33_CR24","doi-asserted-by":"crossref","unstructured":"Olukotun, K., et al.: The Case for a Single-Chip Multiprocessor. In: ASPLOS (1996)","DOI":"10.1145\/237090.237140"},{"key":"33_CR25","unstructured":"Sun Microsystems, Inc. OpenSPARC T1 Micro Architecture Specification, Sun Microsystems, Inc. (2006)"},{"key":"33_CR26","doi-asserted-by":"crossref","unstructured":"Razdan, R., Smith, M.: A high-performance microarchitecture with hardware-programmable functional units. In: Proc. MICRO (1994)","DOI":"10.1145\/192724.192749"},{"key":"33_CR27","doi-asserted-by":"crossref","unstructured":"Rotenberg, E.: Trace cache: a low latency approach to high bandwidth instruction fetching. In: Proc. MICRO (1996)","DOI":"10.1109\/MICRO.1996.566447"},{"key":"33_CR28","doi-asserted-by":"crossref","unstructured":"Rupp, C.R., et al.: The napa adaptive processing architecture. In: Proc. FCCM (1998)","DOI":"10.1109\/FPGA.1998.707878"},{"key":"33_CR29","doi-asserted-by":"crossref","unstructured":"Sassone, P., Wills, D.: Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication. In: Proc. MICRO (2004)","DOI":"10.1109\/MICRO.2004.16"},{"issue":"5","key":"33_CR30","doi-asserted-by":"publisher","first-page":"465","DOI":"10.1109\/12.859540","volume":"49","author":"H. Singh","year":"2000","unstructured":"Singh, H., et al.: Morphosys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Trans. on Computers\u00a049(5), 465\u2013481 (2000)","journal-title":"IEEE Trans. on Computers"},{"key":"33_CR31","unstructured":"TSMC 90nm Core Library - TCBN90GHP, App. Note - Revision 1.2 (2006)"},{"key":"33_CR32","doi-asserted-by":"crossref","unstructured":"Vassiliadis, S., et al.: The molen polymorphic processor. IEEE Trans. on Computers\u00a053(11) (2004)","DOI":"10.1109\/TC.2004.104"},{"key":"33_CR33","doi-asserted-by":"crossref","unstructured":"Wittig, R., Chow, P.: Onechip: An fpga processor with reconfigurable logic. In: Proc. FCCM (1996)","DOI":"10.1109\/FPGA.1996.564773"},{"key":"33_CR34","unstructured":"Wong, S., et al.: Coarse reconfigurable multimedia unit extension. In: Proc. 9th Euromicro workshop on Parallel and Distributed Processing (1996)"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing - HiPC 2008"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-89894-8_33","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T05:43:13Z","timestamp":1557985393000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-89894-8_33"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008]]},"ISBN":["9783540898931","9783540898948"],"references-count":34,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-89894-8_33","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2008]]}}}