{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,7]],"date-time":"2025-02-07T05:06:18Z","timestamp":1738904778059,"version":"3.37.0"},"publisher-location":"Berlin, Heidelberg","reference-count":12,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540898931"},{"type":"electronic","value":"9783540898948"}],"license":[{"start":{"date-parts":[[2008,1,1]],"date-time":"2008-01-01T00:00:00Z","timestamp":1199145600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008]]},"DOI":"10.1007\/978-3-540-89894-8_47","type":"book-chapter","created":{"date-parts":[[2008,12,16]],"date-time":"2008-12-16T15:22:24Z","timestamp":1229440944000},"page":"541-554","source":"Crossref","is-referenced-by-count":3,"title":["Directory-Based Conflict Detection in Hardware Transactional Memory"],"prefix":"10.1007","author":[{"given":"Rub\u00e9n","family":"Titos","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel E.","family":"Acacio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jos\u00e9 M.","family":"Garc\u00eda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"47_CR1","doi-asserted-by":"crossref","unstructured":"Ananian, C.S., et al.: Unbounded transactional memory. In: Proc. of the 11th Int\u2019l. Symposium on High-Performance Computer Architecture, pp. 316\u2013327 (February 2005)","DOI":"10.1109\/HPCA.2005.41"},{"key":"47_CR2","doi-asserted-by":"crossref","unstructured":"Bobba, J., Moore, K.E., Yen, L., Volos, H., Hill, M.D., Swift, M.M., Wood, D.A.: Performance pathologies in hardware transactional memory. In: Proc. of the 34rd Annual Int\u2019l. Symposium on Computer Architecture (June 2007)","DOI":"10.1145\/1250662.1250674"},{"key":"47_CR3","doi-asserted-by":"crossref","unstructured":"Cao Minh, C., et al.: An effective hybrid transactional memory system with strong isolation guarantees. In: Proc. of the 34th Annual Int\u2019l. Symposium on Computer Architecture (June 2007)","DOI":"10.1145\/1250662.1250673"},{"key":"47_CR4","doi-asserted-by":"crossref","unstructured":"Hammond, L., et al.: Transactional memory coherence and consistency. In: Proc. of the 31st Annual Int\u2019l. Symposium on Computer Architecture, pp. 102\u2013113 (June 2004)","DOI":"10.1109\/ISCA.2004.1310767"},{"key":"47_CR5","doi-asserted-by":"crossref","unstructured":"M. Herlihy and E.\u00a0B. Moss. Transactional Memory: Architectural support for lock-free data structures. In Proc. of the 20th Annual Int\u2019l. Symposium on Computer Architecture, pages 289\u2013301, May 1993.","DOI":"10.1145\/165123.165164"},{"issue":"2","key":"47_CR6","doi-asserted-by":"publisher","first-page":"50","DOI":"10.1109\/2.982916","volume":"35","author":"P.S. Magnusson","year":"2002","unstructured":"Magnusson, P.S., et al.: Simics: A full system simulation platform. IEEE Computer\u00a035(2), 50\u201358 (2002)","journal-title":"IEEE Computer"},{"issue":"4","key":"47_CR7","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","volume":"33","author":"Milo M. K. Martin","year":"2005","unstructured":"Martin, M.M.K., et al.: Multifacet\u2019s General Execution-driven Multiprocessor Simulator (GEMS) toolset. Computer Architecture News, 92\u201399 (September 2005)","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"47_CR8","unstructured":"Moore, K.E., Bobba, J., Moravan, M.J., Hill, M.D., Wood, D.A.: LogTM: Log-based transactional memory. In: Proc. of the 12th Int\u2019l. Symposium on High-Performance Computer Architecture, pp. 254\u2013265 (February 2006)"},{"key":"47_CR9","doi-asserted-by":"crossref","unstructured":"Rajwar, R., et al.: Virtualizing transactional memory. In: Proc. of the 32nd Annual Int\u2019l. Symposium on Computer Architecture, pp. 494\u2013505 (June 2005)","DOI":"10.1145\/1080695.1070011"},{"key":"47_CR10","doi-asserted-by":"crossref","unstructured":"Titos, R., Acacio, M.E., Garc\u00eda, J.M.: Characterization of conflicts in log-based transactional memory (LogTM). In: Proc. of the 16th Euromicro Int\u2019l. Conference on Parallel, Distributed and Network-Based Processing, pp. 30\u201337 (February 2008)","DOI":"10.1109\/PDP.2008.63"},{"key":"47_CR11","doi-asserted-by":"crossref","unstructured":"Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 programs: Characterization and methodological considerations. In: Proc. of the 22nd Annual Int\u2019l. Symposium on Computer Architecture, pp. 24\u201336 (June 1995)","DOI":"10.1145\/225830.223990"},{"key":"47_CR12","doi-asserted-by":"crossref","unstructured":"Yen, L., et al.: LogTM-SE: Decoupling hardware transactional memory from caches. In: Proc. of the 13th Int\u2019l. Symposium on High-Performance Computer Architecture, pp. 261\u2013272 (February 2007)","DOI":"10.1109\/HPCA.2007.346204"}],"container-title":["Lecture Notes in Computer Science","High Performance Computing - HiPC 2008"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-89894-8_47","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,6]],"date-time":"2025-02-06T06:23:56Z","timestamp":1738823036000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-89894-8_47"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008]]},"ISBN":["9783540898931","9783540898948"],"references-count":12,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-89894-8_47","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2008]]}}}