{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,26]],"date-time":"2025-03-26T21:36:06Z","timestamp":1743024966911,"version":"3.40.3"},"publisher-location":"Berlin, Heidelberg","reference-count":14,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540899846"},{"type":"electronic","value":"9783540899853"}],"license":[{"start":{"date-parts":[[2008,1,1]],"date-time":"2008-01-01T00:00:00Z","timestamp":1199145600000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008]]},"DOI":"10.1007\/978-3-540-89985-3_141","type":"book-chapter","created":{"date-parts":[[2008,11,21]],"date-time":"2008-11-21T22:39:50Z","timestamp":1227307190000},"page":"951-954","source":"Crossref","is-referenced-by-count":0,"title":["Pre-synthesis Optimization for Asynchronous Circuits Using Compiler Techniques"],"prefix":"10.1007","author":[{"given":"Sharareh","family":"ZamanZadeh","sequence":"first","affiliation":[]},{"given":"Mehrdad","family":"Najibi","sequence":"additional","affiliation":[]},{"given":"Hossein","family":"Pedram","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"141_CR1","doi-asserted-by":"crossref","unstructured":"Gupta, S., Gupta, R., Dutt, N., Nicolau, A.: Coordinated parallelizing compiler optimizations and high level synthesis. ACM transitions on design of electronic systems\u00a09(4) (October 2004)","DOI":"10.1145\/1027084.1027087"},{"key":"141_CR2","doi-asserted-by":"crossref","unstructured":"Gupta, S., Savoiu, N., Dutt, N.D., Gupta, R.K., Nicolau, A.: Using global code motions to improve the quality of results for high level synthesis. IEEE. Transitions on computer aided design of integrated circuits and systems\u00a023(2) (February 2004)","DOI":"10.1109\/TCAD.2003.822105"},{"key":"141_CR3","doi-asserted-by":"crossref","unstructured":"Nicolau, A., Novack, S.: Trailblazing: A hierarchical approach to percolation scheduling. In: International conference on parallel processing (1993)","DOI":"10.1109\/ICPP.1993.181"},{"key":"141_CR4","doi-asserted-by":"crossref","unstructured":"Streedhar, V.C., Gao, G.R., Lee, Y.-F.: Incremental computation of dominator trees. ACM Trans. Program. Languages and syst.\u00a019, 2 March (1997)","DOI":"10.1145\/244795.244799"},{"key":"141_CR5","first-page":"269","volume-title":"Proceedings of the Design Automation Conference","author":"S. Gupta","year":"2001","unstructured":"Gupta, S., Savoiu, N., Kim, S., Dutt, N., Gupta, R., Nicolau, A.: Speculation techniques for High level synthesis of control Intensive designs. In: Proceedings of the Design Automation Conference, pp. 269\u2013272. ACM, New York (2001)"},{"key":"141_CR6","unstructured":"Tugsinavisut, A.: Design and synthesis of concurrent asynchronous systems. The dissertation for the degree doctor of philosophy (electrical engineering) in university of southern California (December 2005)"},{"key":"141_CR7","unstructured":"Asynchronous group of Amir Kabir University: Design and Implementation of Synthesis toolset for asynchronous and GALS circuits. Persia. Technical report to industrial and mines ministry of Iran"},{"key":"141_CR8","unstructured":"Saleh, K.: Hardware Architectures for Reed-Solomon Decoders. Technical Report, Amir kabir University of Technology (January 2003)"},{"key":"141_CR9","volume-title":"Reed-Solomon Codes and Their Applications","author":"S. Wicker","year":"1994","unstructured":"Wicker, S., Bhargava, K.: Reed-Solomon Codes and Their Applications. IEEE Press, Los Alamitos (1994)"},{"key":"141_CR10","unstructured":"Seifhashemi, A., Pedram, H.: Verilog HDL, a Replacement for CSP. In: 3rd ACiD-WG Worksop FP5, FORTH, Heraklion, Crete, Greece (January 2003)"},{"key":"141_CR11","doi-asserted-by":"crossref","unstructured":"Seifhashemi, A., Pedram, H.: Verilog HDL, Powered by PLI: a suitable Framework for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction. In: Proc. Of 40th DAC, Anneheim, CA, USA (June 2003)","DOI":"10.1145\/775914.775917"},{"key":"141_CR12","unstructured":"Wong, G.: High-Level: Synthesis and Rapid Prototyping of Asynchronous VLSI Systems, PhD thesis, California Institute of Technology (May 2004)"},{"key":"141_CR13","doi-asserted-by":"crossref","unstructured":"Morel, E., Renvoise, C.: Global optimization by suppression of partial redundancies. Communication of ACM\u00a022(2) (February 1979)","DOI":"10.1145\/359060.359069"},{"key":"141_CR14","doi-asserted-by":"crossref","unstructured":"Niknahad, Ghavami, Najibi, Pedram: A power estimation methodology for QDI asynchronous circuits based on high-level simulation. In: IEEE computer society annual symposium on VLSI (ISVLSI 2007), pp. 471\u2013472 (2007)","DOI":"10.1109\/ISVLSI.2007.15"}],"container-title":["Communications in Computer and Information Science","Advances in Computer Science and Engineering"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-89985-3_141","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,20]],"date-time":"2019-05-20T21:32:30Z","timestamp":1558387950000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-89985-3_141"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008]]},"ISBN":["9783540899846","9783540899853"],"references-count":14,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-89985-3_141","relation":{},"ISSN":["1865-0929","1865-0937"],"issn-type":[{"type":"print","value":"1865-0929"},{"type":"electronic","value":"1865-0937"}],"subject":[],"published":{"date-parts":[[2008]]}}}