{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T07:47:17Z","timestamp":1725522437512},"publisher-location":"Berlin, Heidelberg","reference-count":34,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540929895"},{"type":"electronic","value":"9783540929901"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-540-92990-1_18","type":"book-chapter","created":{"date-parts":[[2008,12,23]],"date-time":"2008-12-23T06:36:15Z","timestamp":1230014175000},"page":"231-247","source":"Crossref","is-referenced-by-count":4,"title":["Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors"],"prefix":"10.1007","author":[{"given":"Yang","family":"Ding","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mahmut","family":"Kandemir","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mary Jane","family":"Irwin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Padma","family":"Raghavan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"18_CR1","unstructured":"Applications of optimization with Xpress-MP, http:\/\/www.dashoptimization.com\/"},{"key":"18_CR2","unstructured":"Intel 45nm hi-k silicon technology, http:\/\/www.intel.com\/technology\/architecture-silicon\/45nm-core2\/"},{"key":"18_CR3","unstructured":"International technology roadmap for semiconductors (2005), http:\/\/public.itrs.net\/"},{"key":"18_CR4","unstructured":"NAS NPB benchmarks 3.2, http:\/\/www.nas.nasa.gov\/Software\/NPB\/"},{"key":"18_CR5","unstructured":"Virtutech Simics 3.0, http:\/\/www.virtutech.com\/"},{"key":"18_CR6","doi-asserted-by":"crossref","unstructured":"Balakrishnan, S., Rajwar, R., Upton, M., Lai, K.: The impact of performance asymmetry in emerging multicore architectures. In: Proceedings of International Symposium of Computer Architecture (2005)","DOI":"10.1109\/ISCA.2005.51"},{"key":"18_CR7","doi-asserted-by":"crossref","unstructured":"Banerjee, N., Karakonstantis, G., Roy, K.: Process variation tolerant low power DCT architecture. In: Proceedings of Design, Automation and Test in Europe (2007)","DOI":"10.1109\/DATE.2007.364664"},{"key":"18_CR8","doi-asserted-by":"crossref","unstructured":"Becchi, M., Crowley, P.: Dynamic thread assignment on heterogeneous multiprocessor architectures. In: Proceedings of Computing Frontiers (2006)","DOI":"10.1145\/1128022.1128029"},{"key":"18_CR9","doi-asserted-by":"crossref","unstructured":"Borkar, S.: VLSI Design Challenges for Gigascale Integration. In: Proceedings of International Conference on VLSI Design (2005)","DOI":"10.1109\/ICVD.2005.171"},{"key":"18_CR10","doi-asserted-by":"crossref","unstructured":"Borkar, S.: Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro.\u00a025(6) (2005)","DOI":"10.1109\/MM.2005.110"},{"key":"18_CR11","doi-asserted-by":"crossref","unstructured":"Bronevetsky, G., Marques, D., Pingali, K., Szwed, P., Schulz, M.: Application-level checkpointing for shared memory programs. In: Proceedings of Architecture Support for Programming Languages and Operating Systems (2004)","DOI":"10.1145\/1024393.1024421"},{"key":"18_CR12","doi-asserted-by":"crossref","unstructured":"Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: Proceedings of International Symposium of Computer Architecture (2000)","DOI":"10.1145\/339647.339657"},{"key":"18_CR13","doi-asserted-by":"crossref","unstructured":"Cain, J.P., Zhang, H., Spanos, C.J.: Optimum sampling for characterization of systematic variation in photolithography. In: Proceedings of SPIE, vol.\u00a04689 (2002)","DOI":"10.1117\/12.473480"},{"key":"18_CR14","unstructured":"Choi, M.: Modeling of deterministic within-die variation in timing analysis, leakage current analysis, and delay fault diagnosis. School of Electrical and Computer Engineering Theses and Dissertations, Georgia Institute of Technology (2007)"},{"key":"18_CR15","doi-asserted-by":"crossref","unstructured":"Donald, J., Martonosi, M.: Power efficiency for variation-tolerant multicore processors. In: Proceedings of International Symposium of Computer Architecture (2006)","DOI":"10.1145\/1165573.1165645"},{"key":"18_CR16","doi-asserted-by":"crossref","unstructured":"Fetzer, E.S.: Using adaptive circuits to mitigate process variations in a microprocessor design. IEEE Design & Test\u00a023(6) (2006)","DOI":"10.1109\/MDT.2006.159"},{"key":"18_CR17","unstructured":"Gonzalez, R., Horowitz, M.: Energy dissipation in general purpose microprocessors. In: Proceedings of Internationl Symposium on Low Power Electronics (1995)"},{"key":"18_CR18","doi-asserted-by":"crossref","unstructured":"Humenay, E., Tarjan, D., Skadron, K.: Impact of process variations on multicore performance symmetry. In: Proceedings of Design, Automation and Test in Europe (April 2007)","DOI":"10.1109\/DATE.2007.364539"},{"key":"18_CR19","doi-asserted-by":"crossref","unstructured":"Ipek, E., Kirman, M., Kirman, N., Martinez, J.F.: Core fusion: accommodating software diversity in chip multiprocessors. In: Proceedings of International Symposium of Computer Architecture (2007)","DOI":"10.1145\/1250662.1250686"},{"key":"18_CR20","unstructured":"Jin, H., Frumkin, M., Yan, J.: The OpenMP implementation of NAS parallel benchmarks and its performance. Technical Report\u00a0NAS-99-011 (1999)"},{"key":"18_CR21","doi-asserted-by":"crossref","unstructured":"Kahng, A.B., Park, C.-H., Sharma, P., Wang, Q.: Lens aberration aware timing-driven placement. In: Proceedings of Design, Automation and Test in Europe (2006)","DOI":"10.1109\/DATE.2006.243803"},{"key":"18_CR22","doi-asserted-by":"crossref","unstructured":"Kang, K., Kim, K., Roy, K.: Variation resilient low-power circuit design methodology using on-chip phase locked loop. In: Proceedings of Design Automation Conference (2007)","DOI":"10.1145\/1278480.1278710"},{"key":"18_CR23","doi-asserted-by":"crossref","unstructured":"Kim, C., Sethumadhavan, S., Govindan, M., Ranganathan, N., Gulati, D., Burger, D., Keckler, S.W.: Composable lightweight processors. In: Proceedings of International Symposium on Microarchitecture (2007)","DOI":"10.1109\/MICRO.2007.41"},{"key":"18_CR24","doi-asserted-by":"crossref","unstructured":"Kumar, R., Tullsen, D.M., Jouppi, N.P.: Core architecture optimization for heterogeneous chip multiprocessors. In: Proceedings of Parallel Architecture and Compilation Techniques (2006)","DOI":"10.1145\/1152154.1152162"},{"key":"18_CR25","doi-asserted-by":"crossref","unstructured":"Kumar, R., Tullsen, D.M., Ranganathan, P., Jouppi, N.P., Farkas, K.I.: Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. In: Proceedings of International Symposium of Computer Architecture (2004)","DOI":"10.1109\/ISCA.2004.1310764"},{"key":"18_CR26","doi-asserted-by":"crossref","unstructured":"Liang, X., Brooks, D.: Mitigating the impact of process variations on processor register files and execution units. In: Proceedings of International Symposium on Microarchitecture (2006)","DOI":"10.1109\/MICRO.2006.37"},{"key":"18_CR27","doi-asserted-by":"crossref","unstructured":"Meng, K., Joseph, R.: Process variation aware cache leakage management. In: Proceedings of International Symposium on Low Power Electronics and Design (2006)","DOI":"10.1145\/1165573.1165636"},{"key":"18_CR28","doi-asserted-by":"crossref","unstructured":"Miloji\u010di\u0107, D.S., Douglis, F., Paindaveine, Y., Wheeler, R., Zhou, S.: Process migration. ACM Computer Surveys\u00a032(3) (2000)","DOI":"10.1145\/367701.367728"},{"key":"18_CR29","unstructured":"Roberts, D., Dreslinski, R., Karl, E., Mudge, T., Sylvester, D., Blaauw, D.: When homogeneous becomes heterogeneous: Wearout aware task scheduling for streaming applications. In: Workshop on Operationg System Support for Heterogeneous Multicore Architectures (2007)"},{"key":"18_CR30","doi-asserted-by":"crossref","unstructured":"Shafi, H., Speight, E., Bennett, J.K.: Raptor: integrating checkpoints and thread migration for cluster management. In: Proceedings of International Symposium on Reliable Distributed Systems (2003)","DOI":"10.1109\/RELDIS.2003.1238063"},{"key":"18_CR31","doi-asserted-by":"crossref","unstructured":"Teodorescu, R., Torrellas, J.: Variation-aware application scheduling and power management for chip multiprocessors. In: Proceedings of International Symposium of Computer Architecture (2008)","DOI":"10.1109\/ISCA.2008.40"},{"key":"18_CR32","unstructured":"Thoziyoor, S., Muralimanohar, N., Jouppi, N.P.: CACTI 5.0. Hewlett-Packard technical report HPL-2007-167 (2007), http:\/\/quid.hpl.hp.com:9082\/cacti\/"},{"key":"18_CR33","doi-asserted-by":"crossref","unstructured":"Unsal, O.S., Tschanz, J.W., Bowman, K., De, V., Vera, X., Gonzalez, A., Ergin, O.: Impact of parameter variations on circuits and microarchitecture. IEEE Micro.\u00a026(6) (2006)","DOI":"10.1109\/MM.2006.122"},{"key":"18_CR34","doi-asserted-by":"crossref","unstructured":"Veldema, R., Philippsen, M.: Near overhead-free heterogeneous thread-migration. In: Proceedings of International Conference on Cluster Computing (2005)","DOI":"10.1109\/CLUSTR.2005.347042"}],"container-title":["Lecture Notes in Computer Science","High Performance Embedded Architectures and Compilers"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-92990-1_18","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T12:08:21Z","timestamp":1558008501000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-92990-1_18"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783540929895","9783540929901"],"references-count":34,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-92990-1_18","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}