{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T07:46:38Z","timestamp":1725522398198},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540929895"},{"type":"electronic","value":"9783540929901"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-540-92990-1_9","type":"book-chapter","created":{"date-parts":[[2008,12,23]],"date-time":"2008-12-23T06:36:15Z","timestamp":1230014175000},"page":"95-109","source":"Crossref","is-referenced-by-count":9,"title":["A Flexible Code Compression Scheme Using Partitioned Look-Up Tables"],"prefix":"10.1007","author":[{"given":"Martin","family":"Thuresson","sequence":"first","affiliation":[]},{"given":"Magnus","family":"Sj\u00e4lander","sequence":"additional","affiliation":[]},{"given":"Per","family":"Stenstrom","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"9_CR1","first-page":"69","volume-title":"Proceedings of the 23rd International Conference on Computer Design (ICCD)","author":"M. Reshadi","year":"2005","unstructured":"Reshadi, M., Gorjiara, B., Gajski, D.: Utilizing horizontal and vertical parallelism with a no-instruction-set compiler for custom datapaths. In: Proceedings of the 23rd International Conference on Computer Design (ICCD), pp. 69\u201376. IEEE Computer Society, Los Alamitos (2005)"},{"key":"9_CR2","doi-asserted-by":"crossref","unstructured":"Thuresson, M., Sj\u00e4lander, M., Bj\u00f6rk, M., Svensson, L., Larsson-Edefors, P., Stenstrom, P.: FlexCore: Utilizing exposed datapath control for efficient computing. Journal of Signal Processing Systems (to appear, 2008); Accepted on the 4th of March 2008","DOI":"10.1109\/ICSAMOS.2007.4285729"},{"issue":"5","key":"9_CR3","doi-asserted-by":"publisher","first-page":"12","DOI":"10.1109\/40.877947","volume":"20","author":"J. Huck","year":"2000","unstructured":"Huck, J., Morris, D., Ross, J., Knies, A., Mulder, H., Zahir, R.: Introducing the IA-64 architecture. IEEE Micro.\u00a020(5), 12\u201323 (2000)","journal-title":"IEEE Micro."},{"key":"9_CR4","unstructured":"Kissell, K.: MIPS16: High-density MIPS for the Embedded Market. Silicon Graphics MIPS Group (1997)"},{"key":"9_CR5","unstructured":"Advanced RISC Machines Ltd.: An Introduction to THUMB (March 1995)"},{"key":"9_CR6","doi-asserted-by":"publisher","first-page":"108","DOI":"10.1145\/1216919.1216935","volume-title":"Proceedings of the 2007 ACM\/SIGDA 15th international symposium on Field programmable gate arrays (ISFPGA)","author":"B. Gorjiara","year":"2007","unstructured":"Gorjiara, B., Gajski, D.: FPGA-friendly code compression for horizontal microcoded custom IPs. In: Proceedings of the 2007 ACM\/SIGDA 15th international symposium on Field programmable gate arrays (ISFPGA), pp. 108\u2013115. ACM Press, New York (2007)"},{"key":"9_CR7","unstructured":"Game, M., Booker, A.: CodePack: Code Compression for PowerPC Processors. International Business Machines (IBM) Corporation (1998)"},{"key":"9_CR8","unstructured":"Lefurgy, C.R.: Efficient execution of compressed programs. PhD thesis, Ann Arbor, MI, USA, Chair-Trevor Mudge (2000)"},{"key":"9_CR9","first-page":"218","volume-title":"Proceedings of the Sixth International Symposium on High-Performance Computer Architecture (HPCA)","author":"C. Lefurgy","year":"2000","unstructured":"Lefurgy, C., Piccininni, E., Mudge, T.N.: Reducing code size with run-time decompression. In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture (HPCA), pp. 218\u2013228. IEEE, Los Alamitos (2000)"},{"key":"9_CR10","first-page":"362","volume-title":"Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA)","author":"M.L. Corliss","year":"2003","unstructured":"Corliss, M.L., Lewis, E.C., Roth, A.: DISE: A programmable macro engine for customizing applications. In: Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), pp. 362\u2013373. ACM Press, New York (2003)"},{"key":"9_CR11","doi-asserted-by":"crossref","first-page":"77","DOI":"10.1145\/1062261.1062278","volume-title":"Proceedings of the 2nd conference on Computing Frontiers (CF)","author":"M. Thuresson","year":"2005","unstructured":"Thuresson, M., Stenstrom, P.: Evaluation of extended dictionary-based static code compression schemes. In: Proceedings of the 2nd conference on Computing Frontiers (CF), pp. 77\u201386. ACM Press, New York (2005)"},{"key":"9_CR12","unstructured":"EEMBC, the embedded microprocessor benchmark consortium (2008), http:\/\/www.eembc.org"},{"key":"9_CR13","doi-asserted-by":"crossref","first-page":"322","DOI":"10.1145\/383082.383177","volume-title":"Proceedings of the 2001 International Symposium on Low Power Electronics and Design (ISLPED)","author":"L. Benini","year":"2001","unstructured":"Benini, L., Macii, A., Nannarelli, A.: Cached-code compression for energy minimization in embedded processors. In: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (ISLPED), August 2001, pp. 322\u2013327. ACM Press, New York (2001)"},{"key":"9_CR14","first-page":"113","volume-title":"Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (CASES)","author":"M. Brorsson","year":"2006","unstructured":"Brorsson, M., Collin, M.: Adaptive and flexible dictionary code compression for embedded applications. In: Proceedings of the international conference on compilers, architectures and synthesis for embedded systems (CASES), pp. 113\u2013124. ACM Press, New York (2006)"},{"key":"9_CR15","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"291","DOI":"10.1007\/978-3-540-77560-7_20","volume-title":"High Performance Embedded Architectures and Compilers","author":"R. Levin","year":"2008","unstructured":"Levin, R., Newman, I., Haber, G.: Complementing missing and inaccurate profiling using a minimum cost circulation algorithm. In: Stenstr\u00f6m, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (eds.) HiPEAC 2007. LNCS, vol.\u00a04917, pp. 291\u2013304. Springer, Heidelberg (2008)"},{"issue":"3","key":"9_CR16","doi-asserted-by":"publisher","first-page":"354","DOI":"10.1145\/1013948.1013953","volume":"9","author":"J. Yang","year":"2004","unstructured":"Yang, J., Gupta, R., Zhang, C.: Frequent value encoding for low power data buses. ACM Transactions on Design Automation of Electronic Systems\u00a09(3), 354\u2013384 (2004)","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"9_CR17","first-page":"265","volume-title":"Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"S. Balakrishnan","year":"2003","unstructured":"Balakrishnan, S., Sohi, G.S.: Exploiting value locality in physical register files. In: Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), December 2003, pp. 265\u2013276. IEEE, Los Alamitos (2003)"},{"key":"9_CR18","doi-asserted-by":"crossref","first-page":"13","DOI":"10.1109\/HPCA.1999.744314","volume-title":"Proceedings of the Fifth International Symposium on High-Performance Computer Architecture (HPCA)","author":"D. Brooks","year":"1999","unstructured":"Brooks, D., Martonosi, M.: Dynamically exploiting narrow width operands to improve processor power and performance. In: Proceedings of the Fifth International Symposium on High-Performance Computer Architecture (HPCA), January 1999, pp. 13\u201322. IEEE, Los Alamitos (1999)"},{"key":"9_CR19","first-page":"125","volume-title":"Proceedings of the 2nd International Symposium on Code Generation and Optimization (CGO)","author":"R. Canal","year":"2004","unstructured":"Canal, R., Gonz\u00e1lez, A., Smith, J.E.: Software-controlled operand-gating. In: Proceedings of the 2nd International Symposium on Code Generation and Optimization (CGO), March 2004, pp. 125\u2013136. IEEE, Los Alamitos (2004)"},{"issue":"7","key":"9_CR20","doi-asserted-by":"publisher","first-page":"916","DOI":"10.1109\/TC.2008.28","volume":"57","author":"M. Thuresson","year":"2008","unstructured":"Thuresson, M., Spracklen, L., Stenstrom, P.: Memory-link compression schemes: A value locality perspective. IEEE Transactions on Computers\u00a057(7), 916\u2013927 (2008)","journal-title":"IEEE Transactions on Computers"}],"container-title":["Lecture Notes in Computer Science","High Performance Embedded Architectures and Compilers"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-92990-1_9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,9,28]],"date-time":"2021-09-28T14:04:23Z","timestamp":1632837863000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-92990-1_9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783540929895","9783540929901"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-92990-1_9","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}