{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T08:20:53Z","timestamp":1725524453691},"publisher-location":"Berlin, Heidelberg","reference-count":20,"publisher":"Springer Berlin Heidelberg","isbn-type":[{"type":"print","value":"9783540959472"},{"type":"electronic","value":"9783540959489"}],"license":[{"start":{"date-parts":[[2009,1,1]],"date-time":"2009-01-01T00:00:00Z","timestamp":1230768000000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009]]},"DOI":"10.1007\/978-3-540-95948-9_36","type":"book-chapter","created":{"date-parts":[[2009,1,31]],"date-time":"2009-01-31T15:58:14Z","timestamp":1233417494000},"page":"359-368","source":"Crossref","is-referenced-by-count":0,"title":["Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses"],"prefix":"10.1007","author":[{"given":"Antoine","family":"Courtay","sequence":"first","affiliation":[]},{"given":"Johann","family":"Laurent","sequence":"additional","affiliation":[]},{"given":"Olivier","family":"Sentieys","sequence":"additional","affiliation":[]},{"given":"Nathalie","family":"Julien","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"36_CR1","unstructured":"Courtay, A., Laurent, J., Sentieys, O., Julien, N.: Patent reference BFF 08P0103\/HC"},{"key":"36_CR2","doi-asserted-by":"crossref","unstructured":"Magen, N., Kolodny, A., Weiser, U., Shamir, N.: Interconnect-power dissipation in a microprocessor. In: Proceedings of the International Workshop on System Level Interconnect prediction, pp. 7\u201313 (2004)","DOI":"10.1145\/966747.966750"},{"issue":"4","key":"36_CR3","doi-asserted-by":"publisher","first-page":"490","DOI":"10.1109\/5.920580","volume":"89","author":"R. Ho","year":"2001","unstructured":"Ho, R., Mai, K., Horowitz, M.: The future of wires. Proceedings of the IEEE\u00a089(4), 490\u2013504 (2001)","journal-title":"Proceedings of the IEEE"},{"key":"36_CR4","doi-asserted-by":"crossref","unstructured":"Hirose, K., Yasuura, H.: A bus delay reduction technique considering crosstalk. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 441\u2013445 (2000)","DOI":"10.1145\/343647.343815"},{"key":"36_CR5","doi-asserted-by":"crossref","unstructured":"Shang, L., Peh, L., Jha, N.K.: Dynamic voltage scaling with links for power optimization of interconnection networks. In: Proceedings of the 9th International Symposium on High-Performance Computer Architecture, pp. 91\u2013102 (2003)","DOI":"10.1109\/HPCA.2003.1183527"},{"key":"36_CR6","doi-asserted-by":"crossref","unstructured":"Macchiarulo, L., Macci, E., Poncio, M.: Wire placement for crosstalk energy minimization in address buses. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 158\u2013162 (2002)","DOI":"10.1109\/DATE.2002.998264"},{"key":"36_CR7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-1477-0","volume-title":"Crosstalk Noise Immune VLSI Design Regular Layout Fabrics","author":"S.P. Khatri","year":"2001","unstructured":"Khatri, S.P., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: Crosstalk Noise Immune VLSI Design Regular Layout Fabrics. Kluwer Academic Publishers, Hingham (2001)"},{"key":"36_CR8","doi-asserted-by":"crossref","unstructured":"Taylor, C.N., Dey, S., Zhao, Y.: Modeling and minimization of interconnect energy dissipation in nanometer technologies. In: Proceedings of the 38th Conference on Design Automation, pp. 754\u2013757 (2001)","DOI":"10.1145\/378239.379060"},{"issue":"4","key":"36_CR9","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/54.329448","volume":"11","author":"C.L. Su","year":"1994","unstructured":"Su, C.L., Tsu, C.Y., Despain, A.M.: Saving power in the control path of embedded processors. IEEE Design & Test of Computers\u00a011(4), 24\u201331 (1994)","journal-title":"IEEE Design & Test of Computers"},{"issue":"1","key":"36_CR10","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1109\/92.365453","volume":"3","author":"M.R. Stan","year":"1995","unstructured":"Stan, M.R., Burleson, W.P.: Bus-invert coding for low-power I\/O. IEEE Trans. on Very Large Scale Integration Systems\u00a03(1), 49\u201358 (1995)","journal-title":"IEEE Trans. on Very Large Scale Integration Systems"},{"key":"36_CR11","doi-asserted-by":"crossref","unstructured":"Shin, Y., Chae, S.-I., Choi, K.: Partial bus-invert coding for power optimization of system level bus. In: Proceedings of the International Symposium on Low Power Electronics and Design, pp. 127\u2013129 (1998)","DOI":"10.1145\/280756.280829"},{"key":"36_CR12","doi-asserted-by":"crossref","unstructured":"Komatsu, S., Ikeda, M., Asada, K.: Low power chip interface based on bus data encoding with adaptive code-book method. In: Proceedings of the 9th IEEE Great Lakes Symposium on VLSI, pp. 368\u2013371 (1999)","DOI":"10.1109\/GLSV.1999.757458"},{"key":"36_CR13","doi-asserted-by":"crossref","unstructured":"Benini, L., Micheli, E., Macii, E., Sciuto, D., Silvano, C.: Asymptotic zero-transition activity encoding for address busses in low-power microprocessor based systems. In: Proceedings of the 7th IEEE Great Lakes Symposium on VLSI, pp. 77\u201382 (1997)","DOI":"10.1109\/GLSV.1997.580414"},{"key":"36_CR14","doi-asserted-by":"crossref","unstructured":"Philippe, J.M., Pillement, S., Sentieys, O.: Area efficient temporal coding schemes reducing crosstalk effects. In: Proceedings of the International Symposium on Quality Electronic Design, pp. 334\u2013339 (2006)","DOI":"10.1109\/ISQED.2006.28"},{"key":"36_CR15","doi-asserted-by":"crossref","unstructured":"Kretzschmar, C., Nieuwland, A.K., Muller, D.: Why transition coding for power minimization of on-chip buses does not work. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 10512\u201310517 (2004)","DOI":"10.1109\/DATE.2004.1268897"},{"issue":"1","key":"36_CR16","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1166\/jolpe.2008.152","volume":"4","author":"A. Courtay","year":"2008","unstructured":"Courtay, A., Sentieys, O., Laurent, J., Julien, N.: High-Level Interconnect Delay and Power Estimation. J. Low Power Electronics\u00a04(1), 21\u201333 (2008)","journal-title":"J. Low Power Electronics"},{"issue":"2","key":"36_CR17","doi-asserted-by":"publisher","first-page":"173","DOI":"10.1109\/92.386219","volume":"3","author":"P.E. Landman","year":"1995","unstructured":"Landman, P.E., Rabaey, J.M.: Architectural power analysis: the dual bit type method. IEEE Trans. on Very Large Scale Integration Systems\u00a03(2), 173\u2013187 (1995)","journal-title":"IEEE Trans. on Very Large Scale Integration Systems"},{"issue":"5","key":"36_CR18","doi-asserted-by":"publisher","first-page":"903","DOI":"10.1109\/T-ED.1985.22046","volume":"32","author":"H.B. Bakoglu","year":"1985","unstructured":"Bakoglu, H.B., Meindl, J.D.: Optimal interconnection circuits for VLSI. IEEE Trans. on Electron. Devices\u00a032(5), 903\u2013909 (1985)","journal-title":"IEEE Trans. on Electron. Devices"},{"key":"36_CR19","doi-asserted-by":"crossref","unstructured":"Namalpu, A., Burleson, W.P.: Optimal wire sizing and buffer insertion for low power and a generalized delay model. In: Proceedings of the IEEE International Conference on ASIC\/SOC, vol.\u00a031(3), pp. 437\u2013447 (2001)","DOI":"10.1109\/4.494206"},{"issue":"2","key":"36_CR20","doi-asserted-by":"publisher","first-page":"161","DOI":"10.1109\/TVLSI.2005.863750","volume":"14","author":"G. Chen","year":"2006","unstructured":"Chen, G., Friedman, E.G.: Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. IEEE Trans. on VLSI\u00a014(2), 161\u2013172 (2006)","journal-title":"IEEE Trans. on VLSI"}],"container-title":["Lecture Notes in Computer Science","Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation"],"original-title":[],"link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-540-95948-9_36","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,5,23]],"date-time":"2023-05-23T20:52:16Z","timestamp":1684875136000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-540-95948-9_36"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009]]},"ISBN":["9783540959472","9783540959489"],"references-count":20,"URL":"https:\/\/doi.org\/10.1007\/978-3-540-95948-9_36","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2009]]}}}